Search the 20 jobs at Alphawave IP, Inc.

Principal Engineer in Analog Design at Alphawave Semi responsible for designing analog circuits, mentoring junior designers, defining block-level architecture, and supporting .lib generation and Verilog modelling. Requires 12 years of experience in circuit design, knowledge of FinFET design, high-speed IO, and VLSI, as well as a BTech/MTech/MS in VLSI from a reputed university.

Lead the verification of IP and sub-system, develop necessary verification mechanisms, analyze coverage reports, and support regressions. Work on different protocols like PCIe, DDR4, UCIe, AXI4, and CXS. Hybrid work environment with comprehensive benefits package and diversity & inclusivity initiatives.

Responsible for verification of IP, Block, or Subsystem at Soc Level, generating documentation, analyzing/debugging tasks, developing verification environment, and reporting to Lead Engineer. Requires 7+ years of experience with a Bachelor's/Master's degree in Electrical, Electronics, or Computer Engineering. Must have a good understanding of functional verification flow, worked on IP/Block/SoC level verification, experience with digital verification aspects, System Verilog, Verilog, OVM/UVM methodology, AMBA interface protocols, and simulation/debugging.

Develop firmware for UCIe chiplets, participate in design reviews, mentor junior engineers, work with external vendors, and ensure high-quality releases. Requires 8+ years of experience in embedded systems and proficiency in C/C++ and Python.

Collaborate with HR to gather requirements, configure Workday modules, conduct testing, provide training, support and maintain Workday applications, and stay updated with Workday best practices. Requires 5+ years of HRIS configuration experience and in-depth knowledge of Workday configuration.

Perform physical design and verification tasks for advanced process nodes in ASIC development. Mentor junior team members and oversee project-specific flow setup. Work on high-speed designs and have expertise in FinFET node designs.

As a Senior IP Application Engineer at Alphawave Semi, responsible for validating collaterals with customers designing SoCs using the company's IPs. Engage with front-end design engineers, address customer issues, enable IP integration, and provide application-specific expertise. Manage Solution engineers and collaborate with internal R&D team to improve product offerings. Requirements include Bachelor's/Master's degree in relevant fields, minimum 3-6 years of IP/ASIC experience, domain knowledge of interface protocols, and proficiency in serdes, simulators, timing analysis, firmware, and API-C/DPI-C functions.

Deliver standards-compliant IP blocks, lead ASIC or FPGA projects, refine ASIC development process, create micro-architecture, perform RTL coding, mentor junior engineers, and work closely with verification and back-end team.

Provide 1st line technical support to customers designing with Alphawave Semi's chips, perform RTL simulation, design verification, and diagnose and resolve customer issues during integration and silicon bring up. Bachelor's/Master's degree in Electrical/Electronic Engineering or Computer Science required.

Design and optimize physical layer interfaces for memory systems, collaborate with teams, architect memory interface solutions, and mentor junior engineers. Drive architecture, customer engagement, and team coordination for execution.

Perform physical design and verification tasks for advanced process nodes, manage project-specific ASIC development flow, work on high-speed designs, and have experience with Cadence and Synopsys tools. Minimum 6 years of experience in ASIC/SoC Physical Design required.

Perform hands-on physical design and verification tasks for advanced process nodes in ASIC development. Mentor junior team members and collaborate on full chip design activities. Report to ASIC Design Director.

Design and implement state-of-the-art DFT architecture for efficient test and debug capabilities in semiconductor industry. Mentor junior engineers and lead DFT projects. Benefit from a comprehensive benefits package and a hybrid work environment.

Own project schedules, track milestones, work with team leads, drive internal signoff, define process frameworks for efficient execution, and quality deliverables.

Install, configure, and maintain Linux operating systems and servers, lead system security and data assurance, support HPC clusters, troubleshoot server issues, mentor junior staff, collaborate with teams, and participate in on-call rotations for emergencies.

Alphawave Semi is seeking a Principal Engineer - ASIC Design to accelerate critical data communication in industries like data centers, networking, AI, and autonomous vehicles. The role involves powering product innovation, collaborating with customers, and enabling the next generation of digital technology.

Lead layout design activity, produce high-quality IPs/AMS Blocks/Macros, mentor Junior Analog IC Layout engineers, develop scripts, and work with multiple foundries and tools in the semiconductor industry.

Principal Engineer role in SOC Design at Alphawave Semi, responsible for developing architecture, micro-architecture, bus protocols, peripherals, memory controllers, chip IO design, test plans, verification, synthesis, timing closure, and post-silicon debug. Requires a Bachelor's or Master's degree with 15+ years of experience in SoC architecture and full-chip design. Competitive compensation package, RSUs, hybrid working model, medical insurance, and wellness benefits provided.

Responsible for verification of IP, Block, or Subsystem at Soc Level, generating documentation, analyzing/debugging, developing verification environment, and reporting to Lead Engineer.

Deliver standards-compliant IP blocks for use in OTN, Ethernet, CXL, PCIE FPGAs or ASICs. Lead ASIC or FPGA projects. Mentor junior engineers. Report to Director of Verification.