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Seeking experienced UPF experts to build and validate IP/SOC level power intent definitions for high performance power efficient SOC designs. Responsible for bringing up power intent checking flows, debugging issues, and optimizing for low power. Requires strong communication, interpersonal skills, and scripting abilities in Tcl and Python.

Seeking a Senior Memory Design Engineer to develop custom SRAM memories, Register file memories, and compiled memories. Responsibilities include driving the design and development of custom cells for high performance and low power designs, conducting PPA analysis, equivalence checking, collaborating with various teams, and delivering high-quality design collateral.

Positions are open for full-time in the areas of DFT design from unit level to chip level, involving all aspects of DFT design functions from scan, MBIST, to ATPG. Roles in the areas of CPU and SOC DFT design and verification.