Asic RTL Design Engineer

This role is for one of the Weekday's clients

Min Experience: 6+ years

Location: Bengaluru
JobType: full-time

We are seeking an experienced ASIC RTL Design Engineer with 6–10 years of hands-on experience in RTL design, SoC development, and design verification methodologies. The ideal candidate will have strong expertise in developing robust, synthesizable RTL and a deep understanding of Lint, Clock Domain Crossing (CDC), and SoC integration. You will work closely with architecture, verification, physical design, and other cross-functional teams to deliver high-quality ASIC designs from specification through implementation.

• Design, develop, and maintain high-quality, synthesizable RTL for complex ASIC/SoC designs using Verilog/SystemVerilog.
• Translate architectural and microarchitectural specifications into efficient and scalable RTL implementations.
• Perform comprehensive Lint analysis, identify RTL coding issues, and drive corrective actions to ensure clean and maintainable designs.
• Analyze and resolve Clock Domain Crossing (CDC) issues, including synchronization, clock-domain interfaces, and metastability-related concerns.
• Contribute to SoC integration, including integrating IPs, subsystems, interfaces, clocks, resets, and interconnect components.
• Work with design and verification teams to define interfaces, integration requirements, and functional behavior.
• Debug RTL issues using simulation, waveform analysis, and relevant EDA tools.
• Review RTL and design documentation to ensure compliance with architectural and coding standards.
• Participate in design reviews, code reviews, and technical discussions with cross-functional engineering teams.
• Collaborate with verification engineers to develop verification strategies, identify corner cases, and resolve functional issues.
• Support synthesis, timing, and implementation teams by ensuring RTL meets quality, performance, and integration requirements.
• Investigate design issues throughout the ASIC development lifecycle and implement reliable solutions.

• 6–10 years of experience in ASIC/SoC RTL design.
• Strong proficiency in Verilog/SystemVerilog and synthesizable RTL coding.
• Hands-on expertise with Lint tools and methodologies, including identifying and resolving coding, structural, and design-rule violations.
• Strong practical knowledge of CDC analysis, CDC constraints, synchronizers, clock-domain interfaces, and CDC signoff.
• Proven experience with SoC integration, including IP integration, subsystem integration, clocks, resets, interfaces, and connectivity.
• Understanding of ASIC design flows from RTL development through synthesis and signoff.
• Experience debugging RTL using simulation and waveform analysis.
• Strong understanding of digital design concepts, finite-state machines, pipelines, clocking, reset strategies, and interface protocols.
• Ability to work effectively with design, verification, architecture, and physical design teams.

• Hands-on experience with Reset Domain Crossing (RDC) analysis and methodology.
• Experience with RDC-related synchronization and reset architecture issues.
• Familiarity with industry-standard ASIC EDA tools and RTL quality methodologies.
• Exposure to formal verification, synthesis optimization, timing analysis, or low-power design methodologies.
• Experience working on complex SoC or multi-IP semiconductor designs.

Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.

The ideal candidate is a strong RTL design professional who combines hands-on coding expertise with a solid understanding of Lint, CDC, and SoC integration. You should be comfortable working on complex designs, debugging integration issues, collaborating across engineering teams, and taking ownership of RTL quality from development through signoff.