The ASIC Top-Level Verification Engineer will develop environments and tests for ASIC verification, utilizing hybrid emulation and simulation tools while managing regressions and debugging test cases.
About this opportunity
Join our new ASIC top level verification team.
We specialize in the top-level verification of cutting-edge ASICs that power complex high-performance systems. Our designs are either monolithic ASICs or integrated multi-chip-modules holding several hundreds of processor cores, DSPs as well as ARM cores, tailored hardware accelerator IPs and many high-speed interfaces, including Ethernet, CPRI, and PCIe.
As an ASIC Top-Level Verification Engineer, you'll be part of a team tackling some of the most challenging verification tasks in the industry, ensuring that our ASICs meet our high standards for performance, functionality, and security.
You will play an important role in the team developing environments and/or tests run in SystemC/TLM simulation, RTL environments, hardware emulation, and eventually on Silicon.
What you will do
You will bring
Preferably experience in
.
"All academic credentials must be from recognized and accredited institutions and are further subject to verification."
#BI-Hybrid
Join our new ASIC top level verification team.
We specialize in the top-level verification of cutting-edge ASICs that power complex high-performance systems. Our designs are either monolithic ASICs or integrated multi-chip-modules holding several hundreds of processor cores, DSPs as well as ARM cores, tailored hardware accelerator IPs and many high-speed interfaces, including Ethernet, CPRI, and PCIe.
As an ASIC Top-Level Verification Engineer, you'll be part of a team tackling some of the most challenging verification tasks in the industry, ensuring that our ASICs meet our high standards for performance, functionality, and security.
You will play an important role in the team developing environments and/or tests run in SystemC/TLM simulation, RTL environments, hardware emulation, and eventually on Silicon.
What you will do
- Bringing our ASIC designs into a Hardware emulator.
- Developing transactors to enable hybrid environments or usage of testbench run in simulation
- Together with TLM developers, develop hybrid environments where the ASIC is split so that one part is running emulation and the other part in TLM/SystemC.
- Update and maintain existing emulator platforms running ASIC under development as well as legacy ASICs
- Manage regressions running in emulation and help out solving testcase issues and debug failing tests.
You will bring
Preferably experience in
- Experience of HW Emulation using Siemens Veloce and/or Cadence Palladium.
- Experience in writing transactors.
- TLM / Emulation hybrid environments
- How to enable UPF support
- RTL debugging with experience using Waveform debugging tools from one of the three largest EDA vendors
- Development of C SW targeting embedded system, using SW debuggers for debugging.
- Updating testbenches, like adding VIPs
- It is a plus with basic understanding of UPF and even better with experience from running low power simulations using UPF
.
"All academic credentials must be from recognized and accredited institutions and are further subject to verification."
#BI-Hybrid
Ericsson Bengaluru, Karnataka, IND Office
Ericsson Bengaluru Hub Office
Major tech campus on the Outer Ring Road with offices, food courts and services inside the park. Close to key residential areas, though busy, it’s central to Bengaluru’s tech ecosystem.
Similar Jobs at Ericsson
Cloud • Information Technology • Internet of Things • Machine Learning • Software • Cybersecurity • Infrastructure as a Service (IaaS)
The Senior Test Engineer is responsible for designing, executing test cases, managing defect tracking, and supporting QA testing in Agile environments for Cloud Native Functions.
Top Skills:
Hp-QcJIRAKubernetesLinux
Cloud • Information Technology • Internet of Things • Machine Learning • Software • Cybersecurity • Infrastructure as a Service (IaaS)
Own physical-aware synthesis and constraint development for high-performance, low-power SoC designs. Execute floorplan-driven synthesis, integrate synthesis with P&R, optimize netlists for QoR, run STA (PrimeTime), manage library inputs (Liberty, LEF, UPF/CPF), perform equivalence checks, and drive tape-out readiness while collaborating with RTL, P&R, and DFT teams.
Top Skills:
BistBoundary Scan)CpfDefDesign CompilerDft (ScanFormalityFusion CompilerLefLiberty (.Lib)Place-And-Route (P&R)PtpxPythonSdcSynopsys PrimetimeTclUpf
Cloud • Information Technology • Internet of Things • Machine Learning • Software • Cybersecurity • Infrastructure as a Service (IaaS)
The role involves ASIC top-level verification, including testcase development, running simulations, debugging RTL designs, and defining verification strategies.
Top Skills:
ArmAsicCCpriEda ToolsEthernetPcieSystemcSystemverilogTlmVhdl
What you need to know about the Bengaluru Tech Scene
Dubbed the "Silicon Valley of India," Bengaluru has emerged as the nation's leading hub for information technology and a go-to destination for startups. Home to tech giants like ISRO, Infosys, Wipro and HAL, the city attracts and cultivates a rich pool of tech talent, supported by numerous educational and research institutions including the Indian Institute of Science, Bangalore Institute of Technology, and the International Institute of Information Technology.
