Tylsemi is building and scaling high-impact semiconductor operations. We partner across design, manufacturing, and supply chain to bring silicon from concept to high-volume production with speed, quality, and predictable execution.
Role OverviewAs a CAD/Flow Methodology Development leader at Tylsemi, you will define, build, and scale the EDA infrastructure and design signoff methodologies that enable teams to deliver silicon efficiently and repeatably. This role will be good for 10+ years of experience and is ideal for engineers who combine deep tool/flow expertise with strong cross-functional leadership—turning ambiguous productivity and quality goals into robust, automated, measurable flows used across multiple programs and sites.
What You’ll DoOwn end-to-end methodology for key implementation and signoff flows (front-end through back-end), with clear quality gates, metrics, and release processes
Develop and maintain automated flows for synthesis, STA, P&R, physical verification (DRC/LVS), extraction, EM/IR, timing/power closure, and signoff reporting (scope aligned to your background)
Build reusable infrastructure: Makefiles/Python/Tcl-based automation, job orchestration, regression frameworks, dashboards, and standardized runsets
Drive tool enablement and configuration across EDA vendors (e.g., Synopsys/Cadence/Siemens), including version qualification, best-known methods, and performance tuning
Partner with design, PD, verification, DFT, packaging, and product engineering to define signoff criteria, checklists, and tapeout readiness reviews
Create scalable collateral: flow documentation, onboarding guides, templates, reference designs, and training for new teams and new nodes
Debug and root-cause flow issues (tool bugs, runset problems, environment drift, corner setup, library/constraint issues) and drive fixes to closure
Establish and track KPIs (runtime, QoR, convergence rate, violation trends, tapeout escapes) and continuously improve cycle time and first-pass success
Support multi-site execution with reproducible environments, access control, compute strategy, and robust release management
10+ years of experience in CAD, design methodology, or physical design/STA with significant flow ownership (scope aligned to experience level)
Strong understanding of digital implementation and signoff concepts: constraints (SDC), timing closure, CDC/RDC considerations, power intent (UPF/CPF), physical verification, extraction, and signoff correlation
Proven ability to build production-grade automation and infrastructure (Python, Tcl, shell, Make/CMake, Git-based workflows; CI/regressions a plus)
Experience qualifying and supporting EDA tools and flows across multiple projects, including versioning, runset management, and reproducibility
Ability to translate engineering pain points into scalable methodology, with clear documentation and measurable outcomes
Strong debugging skills across tool logs, QoR deltas, environment issues, and cross-team integration problems
Clear communication and high ownership in cross-site, cross-functional environments
EDA CAD/flow development
Design methodology and signoff flows
Automation/scripting (Python/Tcl/shell)
Tool enablement and regression infrastructure
Cross-functional technical leadership
Hands-on experience with advanced-node considerations (multi-corner/multi-mode scale, variation, DFM, reliability signoff, foundry collateral integration)
Experience with compute/grid orchestration (LSF/SLURM/Kubernetes), containerized environments, and reproducible builds
Flow integration for formal/CDC, low-power verification, DFT signoff, or mixed-signal/AMS-adjacent signoff needs
Experience building QoR/runtimes dashboards and automated tapeout readiness reporting
Prior ownership of tapeout-critical signoff checklists and release processes across multiple programs
Teams run consistent, reproducible flows with clear signoff criteria and minimal manual intervention
Tapeout readiness is predictable: fewer late surprises, faster convergence, and strong correlation across tools and stages
Automation and regressions catch issues early (environment drift, runset changes, library/constraint problems) before they impact schedules
Cycle time improves measurably through runtime optimization, standardized methodology, and reusable collateral
Cross-functional partners trust the flow: documentation is clear, support is responsive, and releases are well-managed
Bengaluru, India
San Jose, CA
10+ years (scope and ownership will be aligned to experience level).
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