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Alphawave IP, Inc.

Engineer II - Design Verification

Posted 2 Days Ago
Be an Early Applicant
Bangalore, Bengaluru, Karnataka
Mid level
Bangalore, Bengaluru, Karnataka
Mid level
The Design Verification Engineer will lead the verification of new customer features, review design specifications, build testbenches, and analyze test failures. The role involves collaborating with multiple teams, integrating third-party VIPs for compliance testing, and contributing to the improvement of verification methodologies.
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The Opportunity


We're looking for the Wavemakers of tomorrow.

Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.

Our IP Scaling (IPS) organization is focused on creating customized IP for Alphawave Semi’s expanding customer base. We deliver industry-leading high-speed interconnect solutions tailored to specific requirements across a wide variety of use-cases including High Performance Computing and Artificial Intelligence. We are looking for an enthusiastic Design Verification Engineer to join our fun and dynamic team of talented innovators.

What you’ll do:

  • Own the end-to-end verification of new customer features
  • Review design specifications and devise verification plans
  • Build testbenches and analyze test failures to uncover design bugs
  • Facilitate bit-matching of RTL design and MATLAB system models
  • Integrate 3rd party VIPs for compliance testing of standard protocols
  • Build releases of our design IP for customers
  • Support post-silicon validation and bring-up activities
  • Take on opportunities to lead, plan, and coordinate tasks with team members
  • Collaborate closely with Design, Systems, Analog, FW, and PD teams
  • Contribute towards the continuous improvement of verification methodologies and processes

What you’ll need:

  • 3+ years of ASIC design verification experience
  • An applied understanding of UVM and verification techniques
  • Experience with constrained-random verification in SystemVerilog and UVM
  • Formal Verification, and Power-aware UPF verification techniques
  • Tools/Languages - SystemVerilog, UVM, Python, Perl, C/C++, GNU Make
  • Verification experience in SerDes PHY, DSP, and Analog mixed signal is desirable
  • Knowledge in Ethernet and PCIe standards is desirable
  • Proven effective communication and organizational skills

Diversity & Inclusivity

Alphawave Semi is based in one of the most diverse countries in the world. This includes differences related to race, ethnicity, national origin, gender, gender expression and presentation, sexual orientation, religion, age, ability and socioeconomic status. To us, diversity is one of our strongest assets to our organization. We commit ourselves to promoting the recognition and appreciation of our diverse and rich culture. We believe it is critical to our success to promote freedom of thought and opinion in a respectful environment. Our decisions are rooted in respectfully considering each other’s thoughts and opinions and working towards a greater common goal.

Accommodation

Alphawave Semi is an equal opportunity employer and welcomes applications from all qualified individuals, including visible minorities, Indigenous People, and persons with disabilities. We welcome and encourage applications from people with disabilities. If, as a qualified job applicant, you request an accommodation, Alphawave Semi will consult with you to provide reasonable accommodations according to your specific needs. If you wish to make a request, you will be provided an opportunity if you’re application is selected to proceed in our hiring process.

Top Skills

C/C++
Perl
Python
Systemverilog
Uvm

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