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Altera (altera.com)

FPGA Silicon Design Verification Engineer

Reposted 5 Hours Ago
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In-Office
Bengaluru, Bengaluru Urban, Karnataka
Senior level
In-Office
Bengaluru, Bengaluru Urban, Karnataka
Senior level
As a verification engineer, you will design test strategies, build UVM infrastructure, analyze failures, and create test plans for functional correctness.
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Job Details:

Job Description:

Altera, an Intel Company, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. 

 

As a verification engineer you will work closely with design teams to architect effective and efficient testbench and verification strategies to promote effective debug and failure detection; build UVM infrastructure including monitors, drivers, and scoreboards; produce functional coverage and code coverage; monitor dashboards and regressions; analyze root cause; develop constrained random stimulus and shape content to effectively stress the design space; and create test plans to ensure functional correctness.

Qualifications:

You must possess the minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

 

Minimum Qualifications:

 

• Bachelor's Degree in Electrical Engineer, Computer Engineering, or related field.

 

Minimum of 5Y of experience in the following:

        Experience with SystemVerilog.

        Experience with UVM or OVM methodology.

        Experience with scripting perl/Python

 

Preferred Qualifications:

 

• Master’s Degree in Electrical Engineer, Computer Engineering, or related field.

• Experience with using C/C++ models as golden models to compare with RTL.

• Experience with code coverage.

• Experience with functional coverage.

• Experience with X-propagation.

• Experience with multiple RTL simulators.

• Experience with regression testing.

• Experience creating components that are reusable from block to top.

• Experience in Ethernet/PCIE/AXI/DDR protocols is an added advantage.

Job Type: Regular

Shift:Shift 1 (India)

Primary Location:Bengaluru, Karnataka, India

Additional Locations:

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Top Skills

Axi
C
C++
Ddr
Ethernet
Ovm
Pcie
Perl
Python
Rtl
Systemverilog
Uvm

Altera (altera.com) Bengaluru, Karnataka, IND Office

872d1 Hal 3 Stage Michael Palya Road, Bengaluru, Karnataka, India, 560075

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