IP Design Engineer/Lead

Job Details:

Job Description: 

Job Description:
Creates quality Pre-Silicon Validation collaterals using UVM System Verilog/SystemC and integrates it with the emulation/FPGA model. Tests and debugs the emulation/FPGA model and collaterals for validation readiness. Defines and develops new capabilities and HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-silicon and post-silicon functional and performance validation as well as SW development/validation. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. Interfaces with and provides guidance to Pre-Silicon Validation teams for optimizing pre-silicon validation environments, test suites and methodologies for emulation efficiency. Develops and applies automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization.
Job Experience:
Technical experience in verification of RTL-based digital systems with very good understating of various system level flows
Experience leading development of verification architecture based on evolving requirement from IP/SOC customers
Experience with RTL design, Verilog and simulation, debug tools such as Verdi, System Verilog/SystemC based verification techniques.
Experience in debugging and isolation techniques including writing checkers, monitors, assertions and necessary DPI interfaces for co-emulation environments
Experience in SW Programming/scripting and debug such as C, C++, Perl, Python
Work experience creating a self-checking emulation/simulation test bench
Highly proficient in UVM techniques for verification
Hands-on experience of emulation and simulation BFM based verification
Good understanding of architectural design documents(micro-architecture documents, integration documents)
Preferably good understanding of emulation/simulation platform with major vendors (Synopsys, cadence )
Protocol knowledge : PCIE, CXL, UCIe, CHI, DDR
Good understanding of CPU architecture (Intel/AMD/Arm/GPU)
Highly proficient with coherent, non-coherent and concurrent traffic validation
Experience with emulation based systems such as Synopsys ZeBu, Cadence Palladium or Mentor Graphic Veloce
Experience in building emulation based models for large scale designs is a plus
Job Responsibilities:
Work closely with peers in architecture, design and verification teams
Should be able to review the IP teams requirements, come up with verification plan, test plan, micro-arch, identify scenarios and design intent and develop verification strategies which can ensure defect free IP's
Maintain generic emulation-based verification environment and regression setups for various IP's
Leads activities driving the development of various stimulus to support the emulation based verification of various IP's
Develop and maintain UVM environments for IP interfaces
Work in cross-functional teams to deliver bug free features in a timely manner

Qualifications:

Job Type:Experienced Hire

Shift:Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Business group:The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.