Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Key Responsibilities
- Lead static and dynamic IR drop analysis, signal/power electromigration (EM) verification, and self-heat analysis from block level to full-chip sign-off
- Define and implement robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
- Collaborate with Physical Design teams to define optimal power grid structures, via pillars, and strap distributions to minimize voltage drop while maximizing routing resources
- Work closely with Analog/SerDes designers to analyze current profiles and ensure robust power delivery to sensitive high-speed IP blocks
- Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis, optimizing bump patterns and package routing for superior Power Integrity
- Drive root-cause analysis for voltage drop violations and EM risks; propose and implement layout fixes alongside the PD team
- Verify current density rules for ESD protection networks and ensure compliance with foundry reliability constraints
- Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data
Basic Qualifications
- 10+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products
- Expert proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, Totem, or Cadence Voltus)
- Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm), including fin-heating, thermal coupling, and layout-dependent effects
- Solid understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture
- Proven ability to debug complex voltage drop issues, identify "weak spots" in the grid, and drive convergence on large, complex designs
- Proficiency in Python, Tcl, or Perl for flow automation and data parsing
Preferred Experience
- Experience with networking, PCIe, CXL, or large-scale SerDes integration
- Background in Analog/Mixed-Signal EMIR analysis (using Totem or specialized analog flows)
- Experience performing Chip-Package-System (CPS) thermal and power co-simulation
- Familiarity with thermal analysis tools and their interaction with electrical performance
- Prior technical leadership in defining sign-off criteria and margins for high-volume production chips
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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