The Jr DV Engineer will analyze and debug projects, developing testbenches and perform RTL simulation, verification, and power-aware simulation tasks.
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Requirements
- Minimum of a Bachelor’s degree in Electronic/Electrical Engineering, Computer Engineering, or
equivalent.
- Minimum 3 years of experience of related field.
- Strong analysis, debugging skills, and creative in problem solving.
- Motivated, Self-driven and Independent.
- Well verse in System Verilog (OVM/UVM), Scripting (Python/Perl/Shell), RTL simulators,
Interactive debugger, RTL model build, Testbench development, Power-aware simulation,
Coverage-based random constraint simulation, Formal Property Verification
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