Lead Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

'•    Design & synthesize for a complex SerDes IPs in various technology nodes (> 100G rates)
•    Hands-on in STA flow and Low power implementation using CPF/UPF for Mixed-signal Hybrid PHY IPs such as DDR, USB, PCIe / Ethernet .
•    Experience in timing closure of complex datapath designs as well as control FSM ensuring at 2GHz and above at lower geometry nodes
•    Very good in understanding and defining timing constraints and critical high speed path timing closure working with BE teams
•    Good knowledge of structural DFT and at-speed ATPG .
•    Strong knowledge on complete Implementation flows and rigorous checks before delivery to other teams or customers ex- LINT, SDC, CDC, DFT, Low power and trial PnR

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