Lead Design Verification Engineer - CXL/PCIe

Senior Design Verification Engineer

We are seeking talented Design Verification Engineers  with proven expertise in industry-standard protocols such as PCIe and CXL. You will play a key role in the functional verification of designs, from developing block-level and system-level verification plans to writing test sequences, executing tests, and collecting and closing coverage.

Responsibilities:

· Develop and execute block-level and system-level verification plans.

· Write and execute test sequences, and collect and close coverage.

· Collaborate with RTL designers to debug failures and refine verification processes.

· Utilize coding and protocol expertise to contribute to functional verification.

· Develop user-controlled random constraints in transaction-based verification methodologies.

· Write assertions, cover properties, and analyze coverage data.

· Create VIP abstraction layers for sequences to simplify and scale verification deployments.

Basic Qualifications:

· Minimum of 6 years’ experience in supporting or developing complex SoC/silicon products for server, storage, and/or networking applications.

· Strong academic and technical background in Electrical Engineering or Computer Engineering (Bachelor’s degree required, Master’s preferred).

· Professional attitude with the ability to prioritize tasks, prepare for customer meetings, and work independently with minimal guidance.

· Knowledge of industry-standard simulators, revision control systems, and regression systems.

· Entrepreneurial, open-minded behavior and a can-do attitude, with a focus on customer satisfaction.

Required Experience:

· Interpreting PCIe/CXL standard protocol specifications to develop and execute verification plans in simulation environments.

· Experience using Verification IPs from third-party vendors for PCIe/CXL, focusing on Gen3 or above.

· Ability to independently develop test plans and sequences in UVM to generate stimuli.

· Experience writing assertions, cover properties, and analyzing coverage data.

· Developing VIP abstraction layers for sequences to simplify and scale verification deployments.

Preferred Experience:

· Expertise in verifying Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols, including compliance on PCIe/CXL EP/RC.

· Experience with buffering and queuing with QoS on complex NOC-based SoCs.

· Analyzing performance at the system level on switching fabrics.

Salary:

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.