Lead Engineer Design Verification

Job Description

InnoPhase Inc., DBA GreenWave™ Radios Bangalore is looking for a Lead Engineer - Design Verification to join our fast-paced and motivated team to drive excellence in our 5G products. This role is an excellent opportunity for someone that enjoys driving the critical path and making a significant impact in launching products into the market and winning! 

Key Responsibilities

• Work as part of the Design Verification (DV) team to verify ARM Cortex-based CPU subsystems and/or O-RAN Packet Processer blocks using internally developed Python reference models.
• Work on verification of high-speed interfaces, including PCIe, Ethernet and other SerDes-based interfaces.
• Develop, maintain, and execute SystemVerilog/UVM-based testbench environments to verify RTL designs with bit-accurate and cycle-accurate reference models.
• Develop SoC-level verification environments, reusing verification components developed at IPs/ Subsystem and supporting constrained-random and directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs.
• Verify ARM Cortex-based CPU subsystems, including CPU-to-peripheral communication, memory-mapped register accesses, interconnects, interrupt handling, and CPU interactions with hardware accelerators and networking blocks.
• Develop and execute comprehensive verification plans based on design specifications, collaborating closely with architects, RTL designers, firmware engineers, and cross-functional teams.
• Develop hardware/software (HW/SW) co-verification environments, including testbenches, use cases, APIs, and sequences; execute and debug software-driven verification scenarios.
• Integrate Python/C++ reference models with UVM environments and develop reusable verification components, including drivers, monitors, agents, scoreboards, predictors, and protocol checkers.
• Apply constrained-random verification, functional and code coverage, assertions, and regression testing to identify design issues and achieve verification coverage closure.
• Collaborate with firmware (FW) teams to transition DV sequences and test scenarios into firmware drivers and software-driven validation flows.
• Support hardware emulation, FPGA prototyping, and hardware-assisted verification activities.
• Develop and maintain automated verification and regression flows using Python, Perl, Tcl, and Shell scripting.
• Contribute to advanced verification methodologies, including transaction-level modelling (TLM), emulation/acceleration, and software-driven verification.

Job Requirements

• Bachelor's and/or Master's degree in Engineering (or equivalent) in EC/EE/CS.
• 8+ years of experience in design verification with strong expertise in constrained-random verification, functional and code coverage, assertion-based verification, gate-level simulation (GLS), and reference-model-based verification.
• Proven expertise in developing and verifying IPs, subsystem, and SoC-level designs using SystemVerilog, C/C++ and UVM.
• Strong hands-on experience integrating Python/C++ reference models into SystemVerilog/UVM environments, including developing agents, scoreboards, predictors, and reusable verification components for networking and packet-processing blocks.
• Experience in verifying O-RAN based packet processing systems and/or ARM Cortex-based CPU subsystems including memory-mapped interfaces, interconnects, interrupts, and hardware/software co-verification.
• Hands-on experience with on-chip interconnect protocols, particularly AMBA AXI/ AHB, as well as high-speed interfaces and communication protocols, including PCIe, Ethernet, and SerDes.
• Strong understanding of digital design verification methodologies and the complete verification lifecycle, including test planning, testbench development, test execution, debug, regression, and coverage closure.
• Proficiency in SystemVerilog, Verilog, UVM, and C/C++, along with scripting languages such as Python, Perl, Tcl, and Shell.
• Experience with Cadence vManager for verification metrics extraction, regression management, coverage analysis, and coverage closure.
• Strong debugging and problem-solving skills, including waveform analysis, assertion-based verification, functional coverage, and code coverage analysis.
• Experience with Git for version control, JIRA for issue tracking, and standard documentation and productivity tools.
• Strong communication and collaboration skills, with the ability to work effectively across design, verification, firmware, and system engineering teams.

• Competitive salary and stock options.
• Learning and development opportunities.
• Employer paid health Insurance.
• Earned, Casual, Sick & parental leaves.