Lead DFT Consultant responsible for end-to-end DFT at block and chip level: scan insertion, MBIST/LBIST, IJTAG/BSCAN, ATPG flow and coverage improvement, RTL and gate-level DFT verification, ATE pattern development, silicon bring-up and post-silicon debug, and cross-functional coordination with RTL, PD, verification, and test teams.
Job Title: DFT Consultant
Experience: 6–12 Years
Location: Bangalore
Education: B.E./B.Tech/M.E./M.Tech – ECE / EE / VLSI / Computer Engineering
We are seeking a highly skilled Senior DFT Engineer / DFT Consultant with strong hands-on experience in end-to-end Design-for-Testability (DFT) implementation at block and top levels. The role involves defining test architectures, achieving high ATPG coverage, supporting silicon bring-up, and collaborating closely with cross-functional teams to deliver high-quality silicon.
Key Responsibilities- End-to-end DFT implementation at block and top level including SCAN, MBIST, LBIST, BSCAN, IJTAG
- Define and implement IEEE 1149.1 JTAG & IJTAG architectures
- Perform hierarchical scan insertion and full-chip DFT integration
- Execute complete ATPG flow including coverage analysis and debug
- Drive coverage improvement and LBIST coverage analysis
- Support gate-level simulation (GLS) enablement
- Perform RTL-level DFT verification, lint checks, and equivalence checks
- Develop ATE patterns and support silicon bring-up and post-silicon debug
- Collaborate with RTL, Physical Design, Verification, and Test teams
- Support test strategy and integration for Analog IPs
- Manage multiple designs and ensure timely, high-quality delivery
- 6+ years of hands-on experience in DFT
- Strong expertise in SCAN, MBIST, LBIST, BSCAN, IJTAG, IP test modes
- Proficient in ATPG coverage analysis, DFT debug, and verification
- Experience with EDA tools:
- Siemens Tessent
- Cadence Genus
- Synopsys Fusion Compiler, VCS
- Conformal/Formality, SpyGlass
- Scripting skills in Perl, TCL, and/or Python
- Strong communication, leadership, and cross-functional collaboration skills
- Experience with advanced nodes and low-power DFT techniques
- Exposure to automotive or safety-critical designs
- Full silicon lifecycle experience from RTL to production
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