MIPS is looking for a talented MMU (Memory Management Unit) Design Engineer to join our team focused on developing cutting-edge MMU for RISC-V CPU architectures. The ideal candidate will have a strong foundation in computer architecture, digital design, and memory management principles. This role will involve designing and implementing MMU components tailored for RISC-V processors, ensuring optimal memory access and management.
Key Responsibilities:
- Design and Development:
- Documentation:
- Collaboration:
- Research and Innovation:
Design and implement MMU architectures for RISC-V CPUs, focusing on scalability and performance.
Develop and optimize translation lookaside buffers (TLBs), page tables, and address translation mechanisms specific to RISC-V.
Collaborate with CPU design teams to integrate MMU features seamlessly into the RISC-V architecture.
Prepare detailed design and verification documentation for MMU components.
Contribute to system-level documentation, including architecture overviews, design trade-offs, and implementation guidelines.
Work closely with hardware and software teams to ensure effective integration of the MMU with the RISC-V CPU and associated operating systems.
Participate in design reviews, providing insights and feedback on architectural and implementation decisions.
Stay updated on industry trends and emerging technologies related to memory management and RISC-V CPU design.
Propose and evaluate innovative techniques to enhance memory management capabilities and system performance.
Qualifications:
- Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or a related field.
- Proven experience in MMU design, CPU architecture, or related fields, preferably with experience in RISC-V or similar architectures.
- Strong understanding of computer organization, memory hierarchies, and operating systems.
- Proficiency in hardware description languages (e.g., Verilog) and simulation tools.
- Knowledge of performance analysis tools and techniques.
Preferred Skills:
- Familiarity with memory management techniques (paging, segmentation) and their impact on performance in RISC-V architectures.
- Experience with system-level design and integration in multi-core environments.
- Understanding of security features related to memory management, particularly in the context of RISC-V.
Here’s what you can expect from us:
At MIPS, you’ll be a member of a fast-growing team of technologists that are creating the industry’s highest performance RISC-V processors. Small teams that are part of a non-compartmentalized structure – you’ll be able to understand and have an impact on the bigger picture. A great deal of autonomy, with support from some of the industry’s most experienced CPU engineers. An unlimited growth path – with the right skills, you can decide where you want to expand and grow in your role at MIPS. The opportunity to learn a great deal about the blossoming RISC-V architecture in cutting edge applications with industry leading customers.
At MIPS we provide meaningful benefits programs and products to our associates and their families. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave!
More about us:
MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products.
Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products: the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions.
