Tylsemi is building and scaling high-impact semiconductor operations. We partner across design, manufacturing, and supply chain to bring silicon from concept to high-volume production with speed, quality, and predictable execution.
Role OverviewAs Design Team Member at Tylsemi, you will drive the implementation of digital blocks and/or full-chip designs from netlist to tapeout, partnering closely with RTL, verification, DFT, and signoff teams. This role is open across experience levels (0–30 years) and is ideal for leaders and engineers who enjoy solving complex timing, power, and physical constraints to deliver manufacturable, high-quality silicon.
What You’ll DoOwn physical implementation for blocks/subsystems/top-level: floorplanning, power planning, placement, CTS, routing, and ECO closure
Develop and refine constraints (SDC) in collaboration with RTL/STA; ensure constraints are consistent, complete, and implementation-ready
Drive timing closure across modes/corners, including setup/hold closure, clock quality, and path optimization
Close physical signoff requirements: DRC/LVS, IR drop/EM, antenna, density/fill, and manufacturability checks
Analyze and resolve congestion, utilization, and routing challenges; propose floorplan/architecture improvements when needed
Partner with STA and signoff teams to debug violations and implement clean, reviewable ECOs
Collaborate with DFT on scan/MBIST/DFT constraints and physical requirements; ensure implementation supports testability goals
Support low-power implementation (UPF/CPF intent awareness), multi-voltage domains, level shifters/isolation, and power gating as applicable
Create and maintain flow automation, checks, and reporting (Tcl/Python) to improve predictability and execution speed
Contribute to tapeout readiness: documentation, checklists, design reviews, and root-cause analysis of issues to prevent recurrence
Hands-on experience with ASIC physical design implementation and closure (scope aligned to level of experience)
Strong understanding of digital design fundamentals, timing concepts, and physical effects (RC, crosstalk, clocking, variability)
Ability to debug systematically using reports/logs and to communicate clear problem statements and action plans
Comfort working cross-functionally with RTL, verification, DFT, STA, and signoff to resolve issues efficiently
Good engineering hygiene: version control, reproducible runs, clean documentation, and review-friendly ECO practices
ASIC design
Experience with industry-standard P&R and signoff tools (e.g., Innovus/ICC2, PrimeTime, Calibre/ICV, RedHawk/Voltus or equivalents)
Advanced timing closure experience (useful skew, CRPR, OCV/AOCV/POCV, SI-aware optimization)
Experience with hierarchical design methodologies, chip-level integration, and multi-die/advanced packaging awareness
Low-power implementation experience (UPF), multi-corner multi-mode (MCMM) flows, and power integrity closure
Strong scripting/automation skills (Tcl/Python) and ability to build robust PD utilities and dashboards
Experience with foundry signoff requirements and tapeout checklists for advanced nodes
Predictable execution from floorplan to tapeout with clear milestones, risk tracking, and high-quality deliverables
Clean signoff (timing, DRC/LVS, IR/EM) with well-documented closure strategies and minimal late surprises
Fast, methodical debug and ECO turnaround that reduces schedule risk and improves overall team velocity
Strong collaboration that improves constraints quality, reduces iteration loops, and strengthens tapeout readiness
Bengaluru, India
International
