Physical Design Engineer (Staff / Sr. Staff / Principal)

As a Staff/Sr. Staff/Principal Physical Design Engineer at Velaura AI, you will be responsible for driving the physical implementation and sign-off of critical blocks for next-generation AI and high-performance computing silicon. You will own complex designs from RTL to GDSII, including synthesis, floorplanning, place and route, clock tree synthesis, timing closure, extraction, physical verification, EM/IR, and final sign-off. You will work closely with architecture, RTL, DFT, verification, STA, CAD, and product engineering teams to achieve aggressive Performance, Power, and Area (PPA) targets
on advanced process technologies. This is a highly visible technical role where you will contribute to physical design methodology, optimize implementation flows, solve complex design closure challenges, and help deliver world-class silicon.

Responsibilities

● Own critical design blocks and drive them from RTL to GDSII through synthesis, floorplanning, place and route, timing closure, and sign-off.

● Implement and optimize floorplans, power plans, placement, clock tree synthesis, routing, extraction, and sign-off closure for high-performance designs.

● Drive timing convergence across multiple modes and corners while meeting aggressive frequency, power, area, and schedule goals.

● Work closely with RTL and architecture teams to understand micro-architecture and evaluate feasibility, timing, power, congestion, and area tradeoffs.

● Develop and improve physical design methodologies, implementation recipes, and automation flows to optimize PPA and improve design productivity.

● Perform logic synthesis, placement optimization, CTS, routing, timing ECOs, physical ECOs, extraction, and final sign-off activities.

● Analyze and resolve complex timing, congestion, clocking, signal integrity, power integrity, and physical verification issues.

● Perform physical verification and sign-off checks including DRC, LVS, ERC, antenna, density, metal fill, and layout quality checks.

● Drive EM/IR analysis and collaborate with power integrity teams to ensure robust power delivery and sign-off readiness.

● Work with industry-standard implementation and sign-off tools such as Synopsys Fusion Compiler, Cadence Innovus, PrimeTime, StarRC, Calibre, and Apache RedHawk.

● Create and maintain scripts using Tcl, Perl, Python, or other scripting languages to automate physical design tasks and improve flow efficiency.

● Collaborate with cross-functional teams including RTL, DFT, STA, verification, CAD, packaging, and product engineering to ensure successful silicon delivery.

● Provide technical leadership in physical design closure, methodology development, and advanced-node implementation challenges.

● Mentor engineers and help establish best practices for physical design execution, debug, automation, and sign-off quality.

Required Qualifications

● 8+ years of hands-on experience in physical design implementation and sign-off for complex semiconductor designs.

● Strong experience delivering high-performance blocks from RTL to GDSII in advanced technology nodes.

● Proven experience closing high-performance IPs such as CPU, GPU, VPU, memory controller, DDR, NoC, AI accelerators, or other compute-intensive blocks.

● Excellent understanding of synthesis, floorplanning, placement, CTS, routing, extraction, timing closure, and physical sign-off.

● Strong expertise in Static Timing Analysis, timing constraints, clocking methodologies, multi-corner multi-mode closure, and timing ECO implementation.

● Hands-on experience with physical design and sign-off tools such as Synopsys Fusion Compiler, Cadence Innovus, PrimeTime, StarRC, Calibre, and Apache RedHawk.
 
● Experience with advanced process technologies, preferably sub-5nm nodes.

● Strong understanding of power planning, IR drop, electromigration, signal integrity, congestion analysis, and physical design quality checks.

● Experience debugging complex design closure issues related to timing, congestion, routing, clocks, power, and physical verification.

● Strong scripting skills in Tcl, Perl, or Python for flow automation, data analysis, and productivity improvement.

● Ability to work effectively across multiple projects and with geographically distributed teams.

● Strong analytical, problem-solving, communication, and technical leadership skills.

Preferred Qualifications

● Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, VLSI, or a related discipline.

● Strong understanding of computer architecture, high-performance design concepts, and micro-architecture tradeoffs.

● Experience working on AI accelerators, high-performance compute, networking,CPU, GPU, or memory subsystem designs.

● Experience with low-power implementation flows, UPF-based design methodologies, power domains, level shifters, isolation cells, retention strategies, and power-aware sign-off.

● Good understanding of DFT requirements and their impact on physical implementation, timing, routing, and sign-off.

● Experience developing or improving physical design methodologies, implementation recipes, and CAD automation flows.

● Track record of leading complex block-level or subsystem-level physical design execution through tapeout.

● Ability to mentor junior engineers and provide technical guidance across implementation and sign-off activities.

● Experience with sub-5nm or leading-edge technology nodes.

● Experience with high-performance AI, CPU, GPU, VPU, DDR, NoC, or memory controller designs.

● Experience with hierarchical design implementation and top-level integration.

● Knowledge of advanced clocking techniques, useful skew, clock mesh, or complex CTS methodologies.

● Familiarity with package-aware implementation, bump planning, power grid design, and chip-level integration.

● Experience with timing ECO, functional ECO, metal ECO, and late-stage designclosure.

● Exposure to silicon bring-up, correlation, production support, and post-silicon debug.

● Experience driving physical design methodology improvements and EDA automation.

● Strong technical leadership, mentoring, communication, and cross-functional collaboration skills.

● Passion for solving hard design closure problems and delivering high-quality silicon under aggressive product schedules.

● Background in RTL-to-GDSII physical implementation; high-performance block-level and subsystem-level physical design; synthesis, floorplanning, placement, CTS, routing, and timing closure; Static Timing Analysis and
multi-corner multi-mode design closure; advanced-node physical design implementation; physical verification including DRC, LVS, ERC, antenna, density,and metal fill; power integrity, EM/IR analysis, and sign-off; low-power
implementation and power-aware design closure; physical design methodology, flow development, and automation; or cross-functional silicon development in advanced semiconductor environments.