Join a startup as a Physical Design Engineer, focusing on RTL-to-GDSII implementation, performance optimization, and AI-driven automation.
EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.
Physical Design Engineer (2-4 Years Experience)
We are looking for a high-caliber Physical Design Engineer to join our fast-paced startup team. This role is designed for "top 1%" talent—engineers from tier-1 universities (IIT/NIT/BITS or equivalent) who possess a relentless "go-getter" attitude and the critical thinking skills required to solve complex, next-generation silicon challenges.
If you are eager to move beyond standard digital flows into the future of AI-driven automation, this is your playground.
Key Responsibilities
- End-to-End Ownership: Drive RTL-to-GDSII implementation, including floorplanning, placement, CTS, routing, and physical verification (LVS/DRC/ERC).
- Performance Optimization: Execute high-performance design closure focusing on PPA (Power, Performance, Area) targets in advanced process nodes ( 3nm or below)
- Static Timing Analysis (STA): Perform comprehensive timing closure, including signal integrity, crosstalk analysis, and CPPR (Common Path Pessimism Removal) optimization.
- Power Integrity: Conduct IR-drop analysis (Static/Dynamic) and EM (Electromigration) checks to ensure robust power delivery.
- Innovation: Develop and integrate AI/ML-based automation scripts to optimize the physical design flow and reduce turnaround time.
Qualifications & Requirements
- Education: B.Tech/M.Tech in Electrical/Electronics Engineering from a Top Tier University.
- Experience: 2–4 years of hands-on experience in Physical Design within the semiconductor industry.
- Tool Expertise: Expert-level proficiency in industry-standard tools (Preferred Innovus).
- Technical Depth: Strong understanding of multi-corner multi-mode (MCMM) closure, low-power design techniques (UPF/CPF), and physical verification.
- Mindset: A proven "go-getter" who is diligent, detail-oriented, and capable of taking complete ownership of blocks under tight deadlines.
- The "Plus": Proficiency in Python/Tcl and experience using AI/ML models for EDA tool automation or predictive PPA analysis.
- Location: Bangalore
Similar Jobs
Artificial Intelligence • Semiconductor
Design and deliver signoff-quality silicon layouts for leading-edge AI chips using state-of-the-art EDA tools and in-house flows. Responsibilities include floorplanning, synthesis, place-and-route, timing closure, physical verification, flow/tool enhancement, debugging complex issues, and cross-team collaboration with architecture, packaging, and foundry partners.
Top Skills:
2Nm3Nm7NmClock CtsCowosDesign For TestDrcEda ToolsErcEthernetFloorplanningGdsiiHbmLogical EquivalenceLpddrLvsMemoriesPad RingsPciePlace And RoutePower IntegrityPythonStd Cell LibrariesSynthesisTclTiming AnalysisTsmcUcie
Artificial Intelligence • Hardware • Automation • Manufacturing
Lead SoC execution from specification to silicon, define product and technology roadmaps, architect complex SoCs (NoC, memory, power, micro-architecture), select IP and foundry nodes, drive PPA optimization, govern silicon sign-off (synthesis, DFT, timing closure, tape-out), and coordinate cross-functional teams including design, verification, power, and silicon validation.
Top Skills:
DftFoundry Process NodeIpMemory HierarchiesMicroarchitectureNocPhysical DesignPower ManagementRtlSilicon ValidationSocSynthesisTape-OutTiming Closure
Artificial Intelligence • HR Tech • Professional Services • Software
Lead end-to-end VLSI physical implementation from netlist to GDSII using Cadence Innovus. Perform floorplanning, power planning, placement, CTS, routing, STA-driven timing closure, congestion and power optimization, debug implementation issues, collaborate with RTL/synthesis/verification teams, and support physical sign-off and flow automation.
Top Skills:
Cadence InnovusEmirGdsiiIr-Drop AnalysisMulti-Mode Multi-Corner (Mmmc)PythonShellStatic Timing Analysis (Sta)Tcl
What you need to know about the Bengaluru Tech Scene
Dubbed the "Silicon Valley of India," Bengaluru has emerged as the nation's leading hub for information technology and a go-to destination for startups. Home to tech giants like ISRO, Infosys, Wipro and HAL, the city attracts and cultivates a rich pool of tech talent, supported by numerous educational and research institutions including the Indian Institute of Science, Bangalore Institute of Technology, and the International Institute of Information Technology.
