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Cadence Design Systems

Principal Design Engineer

Job Posted 13 Days Ago Posted 13 Days Ago
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Bangalore, Bengaluru, Karnataka
Senior level
Bangalore, Bengaluru, Karnataka
Senior level
As a Principal Design Engineer at Cadence, you will perform design verification of ASICs, create test plans, and engage in post-silicon validation.
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

  • The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
  • Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
  • The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
  • Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
  • You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Job Description:

  • Design verification of ASICs for Palladium.
  • Position is based in Bangalore.
  • Will have to work at IP, Sub-System and SOC level verification.
  • Test plan creation, functional coverage plan and coding of functional coverage bins.
  • Will be involved in post silicon validation/bring up.

Job Requirements:

  • Strong expertise in Verilog, HVL( SV/Specman e) with UVM/OVM/eRM methodology.
  • Experience in functional coverage/code coverage/assertions development and closure.
  • Experience in test plan creation.
  • Exposure to PCIe and LPDDR verification.
  • Strong debug skills
  • Should be process oriented and have a passion for scripting/automation.
  • Should be a good team player.
  • Effective cross-team communication and documentation skill is strongly preferred.
  • Minimal qualification requires BS/MS degree ECE or CS with 6+ years of experience in related fields.

Behavioral skills required:

  • Must possess strong written, verbal and presentation skills.
  • Good communication and interpersonal skills, demonstrate teamwork and collaboration skills.
  • Ability to establish a close working relationship with both customer peers and management.
  • Explore what’s possible to get the job done, including creative use of unconventional solutions
  • Work effectively across functions and geographies
  • Push to raise the bar while always operating with integrity

We’re doing work that matters. Help us solve what others can’t.

Top Skills

Lpddr
Ovm
Pcie
Specman E
Systemverilog
Uvm
Verilog

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