As a Principal Design Engineer at Cadence, you will be responsible for AMS design specifically focusing on high-speed Memory PHYs. You will define designs, mentor team members, participate in cross-functional discussions, and ensure design quality and project timelines while improving methodologies for efficiency.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Responsibilities:
- Contribute to AMS design for High-speed Memory PHYs.
- Responsible for major sub-system of Memory PHY like Tx, Rx or Clocking
- Understand system specification, define design micro-architecture, and define the design hierarchy.
- Participate in technical discussions with cross function teams
- Fully accountable for AMS design quality and schedule
- Own the design progress, identify potential risks, and mitigation plan for sub-system
- Mentor and provide technical guidance to team working in the projects.
- Contribute to AMS methodology improvements to boost efficiency and productivity.
Requirements/Qualifications:
- Bachelor's/Master's degree in Electronics/Electrical Engineering. Specialization in VLSI/Micro-electronics is preferred.
- 7+ years of Analog Mixed Signal design experience
- Sound knowledge on AMS design techniques and circuit architecture
- Strong experience on high-speed circuits like Tx, Rx, CTLE, Amplifiers, Samplers
- Exposure to Serdes, DDR, HBM technologies
- Should have knowledge on all aspects of Mixed Signal IP design.
- Experience on working with AMS verification and logic designers to achieve AMS circuit requirements
- Hands-on experience on block, IP and system level design.
- Should have involved in designing multiple IPs from Specification to Productization
- Experienced in lab debugs on AMS IPs
- Excellent communication and interpersonal skills, demonstrate teamwork and collaboration skills.
We’re doing work that matters. Help us solve what others can’t.
Top Skills
Vlsi
Similar Jobs
Cloud • Hardware • Software • Semiconductor
The Principal Design Engineer at Cadence will leverage their expertise in computer architecture, embedded programming, and high-performance algorithm design to contribute to innovative technology solutions. Responsibilities include coding, debugging, and optimizing software for embedded processors, while also collaborating with diverse teams and engaging with customers to resolve issues.
Top Skills:
CC++
Cloud • Hardware • Software • Semiconductor
The Senior Principal Design Engineer at Cadence will work on cutting-edge electronic designs, focusing on the architecture of embedded processors, high-performance algorithms, and low-level firmware programming. Responsibilities include writing and debugging software on emulation platforms, collaborating with diverse teams, and engaging with customers for resolution of issues.
Top Skills:
C,C++
Cloud • Hardware • Software • Semiconductor
The Principal Design Engineer will be responsible for leading design verification projects from concept to closure, focusing on functional verification fundamentals and environment development. The role requires a strong background in UVM and System Verilog coding and a minimum of 8 years of experience in design verification.
Top Skills:
SvSystem VerilogUvm
What you need to know about the Bengaluru Tech Scene
Dubbed the "Silicon Valley of India," Bengaluru has emerged as the nation's leading hub for information technology and a go-to destination for startups. Home to tech giants like ISRO, Infosys, Wipro and HAL, the city attracts and cultivates a rich pool of tech talent, supported by numerous educational and research institutions including the Indian Institute of Science, Bangalore Institute of Technology, and the International Institute of Information Technology.
