The Senior DFT Engineer will drive DFT flows for digital designs, work with RTL and PNR teams, and ensure testability and coverage. Responsibilities include defining DFT strategies, creating test vectors, verifying designs, and collaborating across teams while optimizing test processes.
We are looking for an experienced DFT engineer, who is capable of driving the required DFT flows for our digital designs. The ability to work closely with rtl and pnr design team to drive testability is a key feature of this role!
Qualifications
- Hands-on expertise with commercial test generation tools for large complex designs
- Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, MBIST and LBIST
- Experience generating test patterns and analyzing and debugging test failures
- Experience with RTL simulation, synthesis and back end implementation flows
- Experience defining and implementing stuck-at and at-speed techniques
- Experience running test compression flow
- Experience trading off test options with product performance and schedule requirements
- Experience creating and releasing full test programs for device screening
- Test optimization
- Resolve design and flow issues related to DFT, identify potential solutions, and drive execution
Education and Experience
- B.E./B.Tech./M.E./M.Tech in VLSI
- Minimum of 5 years of working experience in DFT flow of a product company.
- Strong fundamentals in digital ASIC design, experience with ASIC test, DFT, and debug
Detailed Responsibilities and Skills
- Define DFT strategy and methodologies
- Define test structures, debug structures, test plans
- Create test vectors, simulate in various modes
- Collaborate with physical design team to close requirements
- Validate DFT requirements are being met
- Work with designers to increase test coverage, debug observability and flexibility
- Verify post-PD designs meet DFT requirements
- Knowledge of full DFT flow (test structure insertion, pattern generation, simulation )
- Hands-on experience with Cadence Genus, Modus tools,
- Should have good understanding of Verilog/VHDL
- Exposure to low power techniques
- Knowledge of TCL and Python scripting is a must
We are looking for trailblazers ...
We strongly believe that the pace of the ongoing hardware revolution will be greatly accelerated by Omni Design’s IP cores and the rapidly emerging semiconductor embedded design business ecosystem.
At Omni Design, we have created an exciting environment with amazing talent across multiple disciplines. We like self-motivated individuals, we encourage initiative, we look for leadership qualities, we value teamwork, we like diversity, and we reward excellence. We are looking for trailblazers to bring Omni Design’s vision to fruition.
If you are interested in making an impact as part of a young, fast growing, cutting edge technology company, please reach out to us.
Omni Design is an equal opportunity employer. We offer excellent compensation. We seek individuals that share our high standards and commitment to excellence.
Top Skills
Atpg
Cadence Genus
Dft Techniques
Ieee 1500 Standard
Jtag
Modus
Python
Tcl
Verilog
Vhdl
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