Senior Engineer I - Design for Test

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

Requirements:

• DFT implementation using MCU16 DFT flow for Tessent

• DFT test pattern generation & verification

• Participate to SoC test Specification

• MBIST RTL generation using MCU16 flow for Tessent

• MBIST test pattern generation & verification

• Support test engineer for production test debug and improvement

• Collaborate with cross functional teams in Design flow improvement

• Overcome design challenges, support achievement of quality goals

Requirements/Qualifications:

Qualifications/Experience:

 Excellent understanding of Design For Test (Scan, ATPG, Memory Bist, Boundary Scan)

• Working experience with Tessent Siemens flow for SCAN , Memory BIST & Boundary Scan

• Understanding of JTAG/IJTAG/1500/1687/1149.1 networks

• Good knowledge in ICL and PDL

• Working experience in Test pattern development, simulation, and debug

• Good knowledge in hardware description languages (e.g. Verilog, VHDL, Verilog-AMS, SystemVerilog)

• Previous experience and proficiency in any one of commonly used scripting languages (Perl, TCL, ..)

• Knowledge of revision control mechanisms

• Superior Written and Verbal Communication skills

• Experience working with cross functional global teams

Preferred Skills:

• Experience with Equivalence Checking tool (Cadence LEC), Synthesis and Static timing analysis, CDC experience.

• Experience with Synospsys tools : DC, FC, TMAX will be also appreciated.

• Experience with QUESTA, Xcelium

• Experience with data management systems (e.g., Subversion, DesignSync)

• Knowledge of Functional Safety / ISO26262 standards

Required Education:

BS or MS in Electrical/Electronic Engineering with 7+ years of experience

Travel Time:

0% - 25%