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Job Description:
The Timing and Communications Business Unit (TCG) provides a broad spectrum of Timing/Clocking products & solutions that enable customers to clock and synchronize their networking systems. TCG team is looking for a highly motivated and talented Senior RTL Design Engineer to work on the digital portion of their ultra-low jitter timing/clocking products. This is a great opportunity for senior design engineers who are passionate about digital design and eager to embark on a rewarding career in hardware design. As an experienced RTL Design Engineer, you will work alongside Analog design and AMS verification engineers on cutting-edge projects and contribute to the creation of innovative product solutions and also gain hands-on experience in ASIC synthesis and validation.
- Collaborate with System architects and Analog design engineers to understand product requirements and specifications
- Assist in the development of RTL (Register-Transfer Level) designs for various digital components and systems
- Contribute to the design and implementation of digital logic, including data paths and control units
- Work with industry-standard hardware description languages (e.g., Verilog, System Verilog) to create and verify RTL code
- Participate in the synthesis and optimization of RTL designs for ASIC implementations
- Work on low power circuit design & DFT flow
- Collaborate with Analog and Mixed-Signal Design and verification teams to achieve first-time right silicon.
- Participate in design of various bus protocols, including SPI, I2C, SMBUS etc.
- Learn and apply best practices in RTL design and verification methodologies
- Stay updated with industry trends and emerging technologies in digital design
Requirements/Qualifications:
- Bachelor's/Master's degree in Electronics Engineering, Electronics and communication Engineering, or a related field with 4+ years of industry experience.
- Strong academic background in digital design, including coursework in digital logic and hardware design.
- Familiarity with hardware description languages (Verilog, System Verilog)
- Eagerness to learn and apply RTL design principles and methodologies
- Familiarity with bus protocols like SPI, I2C & SMBUS.
- Strong problem-solving skills and attention to detail
- Ability to work collaboratively in a team-oriented environment
- Excellent communication skills, both written and verbal
- Enthusiasm for working on complex digital design projects and a passion for innovation
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