Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $12 billion in FY23 and approximately 26,000 people globally working alongside 125,000 global customers, ADI ensures today’s innovators stay Ahead of What’s Possible. Learn more at www.analog.com and on LinkedIn.
Senior Mixed-Signal DV Engineer
About Us
The Engineering Enablement team provides industry-leading tools, methodologies, and support to accelerate product development across the company. This position is part of the Systems Verification and Validation (SVV) team within the Engineering Enablement organization in the CTO Office. SVV is responsible for developing, adopting, and supporting tools, methodologies, and solutions across the entire DV landscape - including Unified Metric-Driven Verification (MDV), SystemVerilog (SV)/UVM-based methods, Mixed-Signal DV, Formal Verification, Functional Safety, Security, Portable Stimulus, and Emulation/Prototyping technologies.
The Opportunity
The SVV team is looking for a self-motivated individual with proven experience in analog behavioral modeling and mixed-signal design verification, along with strong analog design fundamentals to contribute to the Mixed-Signal DV domain. This role will give this individual an opportunity to work with BU's spanning ADI's breadth of industry-leading mixed-signal product portfolio and make significant impact.
Job Responsibilities:
- Develop, deploy, and support Design Verification methodologies with a special focus on Analog/Mixed-Signal and Low-Power
- Champion state-of-the-art circuit simulation and behavioral modeling tools and techniques, and apply to complex A/MS SoC designs with an emphasis on low-power
- Provide high quality proactive application engineering support for both in-house and commercial EDA tools and flows
- Assess, implement, and coordinate the development of new capabilities in the A/MS Design Verification and ensure the success of IC design teams.
Position Requirements
- B. Tech. required, M. Tech. preferred with strong fundamentals in IC circuit design of ADCs, DACs, RF Transceivers, Voltage Regulators etc.
- Proven skills in analog IC design and behavioral modeling are required.
- Proficiency with EDA tools and Design Verification methodologies for low-power, mixed-signal ICs including schematic capture, layout, simulation, familiarity with low-power intent (CPF/UPF/IEEE-1801) and A/MS behavioral modeling is highly desirable.
- Exposure to CAD tool development, experience in software programming (C++, Perl, Python) and behavioral modeling (SystemVerilog RNM, Verilog-AMS, Verilog-A) is a plus.
- Should be able to communicate technical details very effectively with both customers (circuit designers) and peers.
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
Job Req Type: Experienced
Required Travel: No
Shift Type: 1st Shift/Days
