Staff Engineer - RTL Design with Synthesis

Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.

What You'll Do:

• Responsibilities include developing block and full-chip SDC methodology, creating clocking diagrams, analysing and resolving timing issues, and ensuring design closure for performance, power, and area (PPA).

• This role requires expertise in industry-standard tools, scripting for automation, and strong analytical skills, with a deep understanding of timing constraints and chip architecture.

• Developing and closing timing for ASIC designs by creating and managing SDC constraints and collaborating with design and physical design teams.

Responsibilities :

• Develop and implement an efficient methodology for creating and managing block-level and full-chip SDC ( Static Design Constraints) .

• Collaborate with RTL and physical design teams to ensure accurate constraints and successful timing closure across all levels of the design.

• Create and maintain full-chip clocking diagrams and related documentation.

• Analyze and debug timing violations using industry-standard tools, addressing issues from block to top-level.

• Review block-level SDCs and mentor other designers on SDC development best practices.

• Optimize the design for performance, power, and area (PPA) through timing analysis and constraint tuning.

• Participate in design reviews and provide technical expertise on timing-related matters. 

• Education: Bachelor's or Master's degree in Electronics Engineering, or a related field.

• Experience: 8+years of experience with ASIC design flow, including RTL design (Verilog/VHDL) and logic synthesis , with SDC experience being crucial.

• Timing Expertise: Deep understanding of static timing analysis concepts, clocking, and timing exceptions.

• Tools: Proficiency in industry-standard SDC and STA (Static Timing Analysis) tools.

• Scripting: Strong scripting skills (e.g., Python, Perl) for automating tasks and developing methodologies.

• Collaboration: Ability to work effectively with cross-functional teams, including RTL designers, verification engineers, and physical design engineers.

• Problem-solving: Strong analytical and problem-solving skills to identify and resolve complex timing issues. 

Equal Employment Opportunity Statement

Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.