The Senior Formal Verification Engineer will develop and implement formal verification models and assertions, perform model checking, and collaborate with design teams to ensure the design correctness of complex logic components. Responsibilities include improving verification workflows, participating in design reviews, and providing feedback for performance and efficiency improvements.
Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.
Basic Qualifications:
- Bachelor’s degree in Electrical Engineering (EE) is required; a Master’s degree is preferred.
- 3+ years of experience in formal verification or 5+ years in traditional design verification (DV).
- Strong ability to manage and prioritize multiple tasks in a dynamic environment with minimal supervision.
- Entrepreneurial mindset with a proactive, problem-solving attitude. Ability to act quickly with a customer-first focus.
- Excellent collaboration skills, with experience working on cross-functional teams.
Required Experience:
- Develop and implement formal verification (FV) abstractions, models, and assertions, and perform assertion-based model checking to uncover corner-case bugs.
- Identify critical logic components and key micro-architectural properties that ensure design correctness.
- Apply complexity reduction techniques to improve formal property verification and bounded proofs.
- Evaluate the effectiveness of property verification based on design size and complexity.
- Collaborate with designers to implement assertions and formal verification testbenches for unit/block-level RTL.
- Participate in design reviews, providing formal analysis feedback to improve design interfaces and enhance performance, power, and area (PPA).
- Proficiency in System Verilog/Verilog.
- Strong scripting skills in Python or Perl.
Preferred Experience:
- Experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGold.
- Proven expertise in both bug hunting and static proof mechanisms.
- Familiarity with automating formal verification workflows within CI/CD environments.
- Ability to develop detailed formal verification test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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