Senior Formal Verification Engineer

Basic Qualifications:

• Bachelor’s degree in Electrical Engineering (EE) is required; a Master’s degree is preferred.
• 3+ years of experience in formal verification or 5+ years in traditional design verification (DV).
• Strong ability to manage and prioritize multiple tasks in a dynamic environment with minimal supervision.
• Entrepreneurial mindset with a proactive, problem-solving attitude. Ability to act quickly with a customer-first focus.
• Excellent collaboration skills, with experience working on cross-functional teams.

Required Experience:

• Develop and implement formal verification (FV) abstractions, models, and assertions, and perform assertion-based model checking to uncover corner-case bugs.
• Identify critical logic components and key micro-architectural properties that ensure design correctness.
• Apply complexity reduction techniques to improve formal property verification and bounded proofs.
• Evaluate the effectiveness of property verification based on design size and complexity.
• Collaborate with designers to implement assertions and formal verification testbenches for unit/block-level RTL.
• Participate in design reviews, providing formal analysis feedback to improve design interfaces and enhance performance, power, and area (PPA).
• Proficiency in System Verilog/Verilog.
• Strong scripting skills in Python or Perl.

Preferred Experience:

• Experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGold.
• Proven expertise in both bug hunting and static proof mechanisms.
• Familiarity with automating formal verification workflows within CI/CD environments.
• Ability to develop detailed formal verification test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications.