Senior Physical Design Analog Integration Engineer

Job Details:

Job Description: In this role, we are looking for an experienced SOC Analog Engineer to lead Analog Integration for chiplet designs for custom and domain specific products. The chiplets will be leveraged to enable modular design and support multiple products. As part of this team, the candidate will work with leading edge technologies and solutions across multiple domains including SoC multi-die implementations (2.5 and 3D), power delivery, leading edge memory technologies, innovate thermal solutions, and external vendors. The team will also look at options to enhance product power/performance/area/cost thru improved tools and methodologies.
Responsibilities will include but are not limited to:
� Drive all aspects of analog integration domain, including analog route implementation/extraction/verification, AIP floor planning, PKG interactions w/ analog IOs, power framework simulations, ESD planning/verification, MIM, and GPIO planning
� Collaborate across multiple teams/stakeholders to create optimal solutions across Platform/PKG/SoC
� Create, run, and analyze simulations for design and verification of analog circuitry such as amplifiers, reference systems, ESD, and high-speed Rx/Tx circuitry
� Scope process technologies and enable integration of Analog IP and silicon supplied by external vendors
� Support post-silicon activities in debug and failure analysis for analog and power delivery
The ideal candidate should exhibit the following behavioral traits/skills:
� Have expertise with domain specific signoff tools including: HV Openrail, Redhawk, LV/antenna checks.
� Have experience with IP design, packaging and delivery methodologies and flows as well as generation of IP integration documents and datasheets

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
� Bachelor's or Master's degree in Computer Science, Computer Engineering or Electrical Engineering.
� 6+ years of Analog design experience including Analog integration and AIP design
� 6+ years experience with SoC analog requirements, including analog distributions, and ESD.

Preferred Qualifications:
� Experience with Design tools and methods.
� Full chip integration, die-to-die and package integration experience.
� 2.5/3D design experience and implications on analog design.

� Experience with power delivery design and flows

Job Type:Experienced Hire

Shift:Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Business group:The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.