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GlobalFoundries

Principal Physical Design Engineer

Job Posted 12 Days Ago Posted 12 Days Ago
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Bangalore, Bengaluru Urban, Karnataka
Mid level
Bangalore, Bengaluru Urban, Karnataka
Mid level
The Senior Physical Design Engineer will handle physical design implementation, timing closure, and verification at block level, ensuring proper integration and functionality of semiconductor designs.
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Title: Principal Physical Design Engineer

About GlobalFoundries

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

Your Job:

The engineer will be responsible for doing physical design implementation, timing closure, and Physical verification at the block level.

Job Responsibilities:

Execute block-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs.

Schematic (LVS) checks, Antenna checks. Need experience in full chip physical design such as integration of blocks, top level floorplanning, clock tree synthesis, timing constraints development and convergence. I/O placement and constraints.

Experience with UPF coding and modification as per design requirements. Need to take care of all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out.

Should be able to interface with the Front End Design team to resolve Design Issues Must possess hands on experience in P&R; from RTL to GDS including timing closure and Physical verification. Design experience in all aspects of physical design.

Proficient and powerful user of Synopsys ICC/ICC2, Cadence innovus. Experience in Mentor Calibre tools to run Physical verification Experience in Apache to run EM IR- analysis is a Plus.

Experience in Tcl/ Tk, PERL, Makefile is a Plus Excellent verbal and written communication skill is required.

Excellent interpersonal and analytical skills with an ability to work independently and within a team are required. Highly motivated, excellent team player, and customer oriented.

Experience :

4-6 Years of Physical Design Experience

Qualification :

Bachelor or Master’s degree in Electrical and Electronics engineering.

Required skills and Qualification

Good understanding of low power concepts. Good exposure in Floorplanning, CTS, STA, Physical Verification.

Good understanding of top-level physical design, partitioning and timing constraints, IR Drop.

Basic understanding of timing constraints.

Knowledge in Automation script (TCL, Perl, etc), Auto FuSA would be an added advantage.

GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard.

As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities.

All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.

Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia

 

Top Skills

Apache
Cadence Innovus
Mentor Calibre
Perl
Synopsys Icc/Icc2
Tcl

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