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Marvell Technology

Senior Staff Design Verification Engineer

Job Posted 6 Days Ago Posted 6 Days Ago
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2 Locations
Senior level
2 Locations
Senior level
The role entails overseeing IP/Sub-System Verification, defining test plans, developing testbenches, executing design verification, and debugging simulation failures.
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About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

The Data Centre Engineering Group develops Custom Silicon products tailored for the Data Centre market, focusing on cutting-edge Accelerated Infrastructure solutions for Networking, Switching, Connectivity, and Compute. The team works on high-performance and scalable architectures, ensuring optimized performance, power efficiency, and reliability to meet evolving data center demands. By collaborating across multiple teams, the group delivers best-in-class silicon solutions that drive innovation in next-generation data center applications.

What You Can Expect

  • Responsible for IP/Subsystem Verification.
  • Define Test Plan, Testbench Architecture, and develop testbenches.
  • Execute Design Verification (Testbench/test sequence development, debug, regression, coverage closure, gate-level simulations).
  • Support Silicon bring-up activities.
  • Debug failures in simulation and perform root-cause analysis

What We're Looking For

  • Bachelor’s or Master’s degree in Computer Science, Electrical Engineering with 8+ years of experience in Digital Pre-Silicon Verification.
  • Experience in leading IP, Subsystem, or SoC-level verification.
  • Strong understanding of SoC/Subsystem design verification concepts and architectures.
  • Hands-on experience with Verilog, SV-UVM, and SoC-level testbenches.
  • Experience in setting up and debugging functional and gate-level simulations.
  • Ability to translate functional requirements into verification plans.
  • Proficiency in developing verification environments and regression setups.
  • Expertise in coverage analysis and closure.
  • Strong interpersonal and communication skills.
  • Ability to collaborate and influence design verification methodologies.
  • Quick adaptability to new technologies with strong problem-solving skills.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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Top Skills

Sv-Uvm
Verilog

Marvell Technology Bengaluru, Karnataka, IND Office

Global Technology Park, Tower D, 10th & 11th Floors, Marathahallli - Sarjapur Outer Ring Road, , ,, Bengaluru, India, 560103

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