Senior Staff Physical Design Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

The Marvell Physical Design team is located in our Santa Clara, CA office, and has a long history of successful design tapeouts in advanced process nodes. Our team is made up of both newer and more experienced engineers with a broad depth of physical design engineering experience. Being a part of our team will give you a chance to work on many different aspects of the chip design process, while working alongside some of the best engineers in the industry. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor and data center chips in a leading-edge CMOS process technology.

What You Can Expect

Marvell’s Custom Cloud Solutions Business Unit (CCS) develops cutting-edge semiconductor solutions in the most advanced technologies. Our focus is on solving the most difficult design problems in the areas of AI, data movement, memory/storage, switch, networking, security, and other infrastructure applications. Your tasks will include performing synthesis, place and route, clock tree synthesis, routing, power-signal integrity, and physical verification as well as timing analysis and closure on multiple intermediate and complex logic blocks with IP challenges. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. This role will expose you to partition and chip-level issues to resolve. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree

• Strong understanding of standard RTL to GDS flows and methodology

• Strong proficiency of PD optimization and Routing such as floorplanning, placement, clocking, and routing

• Strong knowledge of placement with complex IP such as DDR, PCIe, etc

• Has been a leader in their physical design block team to report the status of team's block QoR and assist with the team's challenges preferred

• Has some exposure of partition level work

• Has some exposure to Siemens Tessent DFT preferred

• Strong proficiency with EDA tools such as Cadence Innovus / Synopsys Fusion Compiler

• Proficient with Synthesis and Timing EDA tools

• Good scripting skills in languages such as Perl, tcl, and Python.

• Good object-oriented programming skills

• Good understanding of digital logic and computer architecture.

• Knowledge of Verilog/VHDL

• Good communication skills and self-discipline contributing in a team environment

Expected Base Pay Range (USD)

124,420 - 186,400, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected].

Interview Integrity
 

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.
 
Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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