Staff Engineer - DFT

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Marvell switching solutions in DCE team have been driving a change in networks from the traditional methods of simply moving bits to delivering exciting services and applications. By delivering a stream of technical innovations through a diverse set of fast‐growing product lines, Marvell technology is powering the next‐generation network. DCE Switch team is responsible for overall DFX solution implemented in all Marvell Switch products. The team owns DFX Strategy, DFX Architecture, DFX IP and SoC validation pre and post-Si.

What You Can Expect

• Work on all aspects of DFT (Design for Testability) for networking domain products, including architecture, testability strategy, flow, implementation, verification, and post-silicon bring-up.
• Collaborate with DFT team members for feature implementation, integration, and verification in SoCs.
• Work closely with Logic Design, Physical Design, STA, and ATE teams to ensure seamless DFT execution.

What We're Looking For

• Bachelor's/Master's degree in Electronics, Electrical Engineering or related fields and a 5 to 10 years of related professional experience in DFT.
• Strong expertise in Memory BIST with knowledge of memory testing, fault models, and BIST techniques.
• Experience in Tessent MBIST block and SoC implementation.
• Hands-on experience in MBIST simulations, production pattern generation, and mode constraints.
• Cross-functional collaboration with DFT, design, synthesis, physical design, and STA teams.
• Knowledge of JTAG (IEEE 1149.1/6 standards) and post-silicon ramp-up/debug on ATE.
• Experience with gate-level simulations (no timing & SDF-based simulations).
• Proficiency in MBIST insertion tools (Mentor Tessent preferred).
• Additional experience in SCAN, ATPG, and JTAG is a plus.
• Strong Perl/Tcl scripting skills.
• Excellent teamwork, communication, ownership, and responsibility for successful tape-out and post-silicon ramp-up.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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