Sr Principal RTL Design Engineer

Posted 13 Days Ago
Be an Early Applicant
Bangalore, Bengaluru Urban, Karnataka
7+ Years Experience
Cloud • Hardware • Software • Semiconductor
The Role
Looking for a Senior Principal RTL Design Engineer with 12+ years of ASIC design experience. Proficiency in Verilog coding, RTL design, and various interface protocols. Must have knowledge of RTL checks and synthesis flow.
Summary Generated by Built In

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  • 12+ years of experience in ASIC design
  • Proficient in Verilog coding, RTL design and complex control path and data path designs
  • Knowledge of any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, SATA
  • Knowledge of RTL checks ex- LINT, SDC, CDC Familiar with synthesis flow, LEC and timing constraints
  • Experience in writing Verilog testbench and running simulations.

We’re doing work that matters. Help us solve what others can’t.

Top Skills

Verilog
The Company
HQ: San Jose, CA
8,216 Employees
On-site Workplace
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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