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Sr Principal RTL Design Engineer

Posted 2 Days Ago
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Bangalore, Bengaluru, Karnataka
Expert/Leader
Bangalore, Bengaluru, Karnataka
Expert/Leader
The Sr Principal RTL Design Engineer at Cadence will design complex ASICs, with a focus on RTL design using Verilog, while ensuring compliance with various interface protocols and performing timing constraints. The role involves writing Verilog testbenches and running simulations to validate designs.
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  • 12+ years of experience in ASIC design
  • Proficient in Verilog coding, RTL design and complex control path and data path designs
  • Knowledge of any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, SATA
  • Knowledge of RTL checks ex- LINT, SDC, CDC Familiar with synthesis flow, LEC and timing constraints
  • Experience in writing Verilog testbench and running simulations.

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Top Skills

Verilog

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