You will define, develop, and implement DFT architecture in LiDAR SoCs, collaborating with various design teams, and supporting post-silicon bring-up.
About us
Aeva’s mission is to bring the next wave of perception to a broad range of applications from automated driving to industrial robotics, consumer electronics, consumer health, security, and beyond. Aeva is transforming autonomy with its groundbreaking sensing and perception technology that integrates all key LiDAR components onto a silicon photonics chip in a compact module. Aeva 4D LiDAR sensors uniquely detect instant velocity in addition to 3D position, allowing autonomous devices like vehicles and robots to make more intelligent and safe decisions.
Role Overview
As a DFT Lead you will integrate and Optimize Design-For-Test architecture in our LiDar SoCs.
What you’ll do
- Responsible for Defining, Developing and Implementing DFT methodologies for a high-performance LiDAR Chip.
- Owning DFT planning, Insertion, verification and validation.
- Collaborating with RTL Design, Physical Design teams and ASIC vendors to ensure proper test implementation for automotive grade SoC.
- Work closely with IP vendors on proper DFT Implementation of the IPs in SoC.
- Supporting post-silicon bring-up and debug including silicon failure analysis and yield improvement.
- Create and maintain documentation, DFT guidelines and test architecture specification.
What you’ll have
- 12+ Years of experience in developing and implementing DFT architecture and test strategies for complex ASIC/SoC Designs.
- In-Depth knowledge and hands-on experience of industry standard and proprietary DFT techniques, such as, SCAN/ATPG, Built-in-Self Test (MBIST/LBIST) Architecture , JTAG (IEEE 1149.x/1500/1687), Boundary Scan (BSCAN) and compression/decompression technologies on Digital and Mixed Signal SoCs.
- In-Depth knowledge of EDA tools used for DFT, especially Mentor/Synopsys tools.
- Scripting expertise in Python/PERL, TCL, etc
- Experience in RTL coding and SDC creation for DFT Modes.
- Recent Tapeout experience in advanced nodes.
Nice to have
- Familiarity with developing automotive grade silicon with AEC-Q100 qualification and ISO26262
Top Skills
Asic
Boundary Scan
Built-In-Self Test
Dft Methodologies
Jtag
Lidar
Mentor Tools
Perl
Python
Scan/Atpg
Soc
Synopsys Tools
Tcl
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