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Analog Devices

Staff Digital Design Engineer

Reposted 3 Days Ago
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In-Office
Bangalore, Bengaluru Urban, Karnataka
Expert/Leader
In-Office
Bangalore, Bengaluru Urban, Karnataka
Expert/Leader
The Staff Digital Design Engineer is responsible for RTL coding, micro-architecture design, and verification processes within digital subsystems, mentoring junior engineers, and ensuring product compliance with power and performance goals.
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About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).

          

Position: Staff Engineer, Digital Design  
Experience: 10 to 14 years
Education: BE/BS/Mtech/M.E degree in Electrical/Electronics/Computer science from a reputed institute

Location: Bangalore, India
 

►Responsibilities:

  • Translate requirements to design specification by working closely with system architects
  • Translate the design specification to optimal digital micro-architecture
  • RTL coding using Verilog and System Verilog
  • Building reusable sub-systems and systems, and drive automation with hands-on contribution during the integration of IP
  • Manage the complexity of Safety, Security and Low-power as overlays on vanilla sub-system architectures
  • Continuously improve the development and support model employed on Digital Processing sub-systems to ensure a high level of scalability and efficiency in product engagements
  • Support simulation, DFT and silicon verification and validation of sub-systems, test and evaluation of ASIC products and FPGA development systems
  • Meet power, performance and area goals by micro-architecture optimization
  • Work closely with DV team to develop test-plans
  • Front end implementation – Lint/CDC , synthesis, Timing constraint development
  • Work closely with DFT and PD teams for signoff
  • Support Silicon validation
  • Mentor junior design engineers

►Minimum Qualifications:

  • BE/BS/Mtech/M.E degree in Electrical/Electronics/Computer science from a reputed institute
  • 10 years of relevant experience
  • Strong engineering background in embedded system design, including ASIC microarchitecture, computer architecture, SoC architecture, and custom or standard DSP or hardware accelerator microarchitecture
  • Strong hands-on RTL coding experience and debugging skills
  • Digital Subsystem, clocking and full chip integration experience
  • Expertise in timing constraints development and critical path timing closure
  • Experience with silicon and software product development and understanding the product development lifecycle
  • Knowledge of industry standard bus protocols such as AHB, APB, AXI
  • Experience in digital signal processing and Matlab modeling is highly desirable
  • Excellent verbal and written communication skills to work effectively with teams spread geographically
  • Experience in mentoring junior engineers

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: Experienced

          

Required Travel: Yes, 10% of the time

          

Shift Type: 1st Shift/Days

Top Skills

Asic
Dsp
Matlab
Soc
System Verilog
Verilog

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