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Western Digital

Technologist, ASIC Development Engineering (RTL Design)

Posted 6 Days Ago
Be an Early Applicant
Bengaluru, Karnataka
Senior level
Bengaluru, Karnataka
Senior level
The role involves SOC design and implementation with a focus on ASIC macro and micro-architecture activities for storage-based controllers. Responsibilities include RTL design, synthesis, timing analysis, mentoring juniors, and evaluating design trade-offs. Candidates should have strong technical skills in SOC methodologies and low power design, along with a hands-on approach and excellent communication skills.
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Company Description

At Western Digital, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible.

At our core, Western Digital is a company of problem solvers. People achieve extraordinary things given the right technology. For decades, we’ve been doing just that. Our technology helped people put a man on the moon.

We are a key partner to some of the largest and highest growth organizations in the world. From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter and more connected, to powering the data centers behind many of the world’s biggest companies and public cloud, Western Digital is fueling a brighter, smarter future.

Binge-watch any shows, use social media or shop online lately? You’ll find Western Digital supporting the storage infrastructure behind many of these platforms. And, that flash memory card that captures and preserves your most precious moments? That’s us, too.

We offer an expansive portfolio of technologies, storage devices and platforms for business and consumers alike. Our data-centric solutions are comprised of the Western Digital®, G-Technology™, SanDisk® and WD® brands.

Today’s exceptional challenges require your unique skills. It’s You & Western Digital. Together, we’re the next BIG thing in data.

Job Description

SOC Design Engineer - Job Description

You should have strong knowledge and experience with all aspects of the SOC design and implementation flow – including datapath design, low power design, clock and reset schemes, coverage driven verification, synthesis, P&R, STA, DFT, power-islands, floor-planning, CTS, IR-drop – and an understanding of how architecture decisions impact these flows. You will be responsible for developing, contributing, and leading ASIC macro and micro-architecture activities in our storage-based controllers. You should be highly motivated with strong communication skills, attention to detail, and quality oriented. Candidates with a take-ownership attitude will succeed in this role.

it is a hands-on SOC design implementation role.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

  • Strong knowledge in IP/SOC design methodologies.
  • Sound knowledge of RTL/SOC design/integration with Verilog/system Verilog
  • Strong experience in Synthesis, timing, full chip netlist & front-end design tools& flows Low power design
  • Mentoring juniors and enhancing their skill set
  • Expert knowledge on code coverage, functional coverage, Lint, CDC etc
  • Power Analysis based on RTL/Netlist including early power estimation based on previous generation architectures
  • Defining requirements for ASIC design, verification, and physical implementation teams
  • Evaluating area, performance, power, and ease-of-implementation trade-offs between different implementation solutions
  • Reviewing and configuring 3rd party IPs
  • Supporting other teams in the ASIC organization and reviewing their work
  • Supporting product teams with documentation, code-reviews, and silicon debug
  • Continuously finding opportunities for improving design quality and design practices
  •  


    Qualifications

    Qualifications

    • Bachelor/ Master degree in Electronics/VLSI/Micro-Electronics Engineering 
    • 10+ years of ASIC Design/Architecture experience with strong knowledge of USB, SD, PCIe + NVMe and/or UFS in a storage application
    • RTL design experience in Verilog/SystemVerilog
    • Knowledge and experience in various aspects of SOC design, verification, and implementation flows
    • Experience with low-power design techniques
    • Ability to read and understand SW code
    • Understanding of CPU and memory architectures, datapath pipelining mechanisms, distributed system design, ASIC low-power implementations, clock and reset methodologies
    • Excellent Logic design and debug skills; proficiency in protocols like SATA/USB/PCIe; knowledgeable in bus protocols like AHB/AXI/I2C/UART/JTAG/CJTAG
    • Should work with Verification, FW, Validation, Analog, IO, Physical Design, ATE test, Chaz and Quality teams to architect, design and debug

    Additional Information

    Western Digital thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.

    Western Digital is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

    Top Skills

    Rtl
    System Verilog
    Verilog
    HQ

    Western Digital Bengaluru, Karnataka, IND Office

    WMVV+J5H, Kadubeesanahalli, Bengaluru, Karnataka, India, 560103

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