Search the 6 jobs at Astera Labs

Senior Physical Design Engineer with hands-on experience in synthesis, timing closure, formal verification, and full chip ownership. Must have expertise in Cadence and/or Synopsys tools, System Verilog/Verilog, DFT, and scripting in Python or Perl. Knowledge of DFT test coverage, ECO methodologies, and working with IP vendors is required.

Senior DFT Engineer position at Astera Labs working on the next generation of connectivity products. Responsibilities include chip design, verification, gate-level simulations, scripting, and hands-on expertise with test generation tools. Preferred experience with SOC level verification and IEEE standards.

Seeking talented Design Verification Engineers with expertise in industry-standard protocols such as PCIe and CXL. Responsible for developing and executing verification plans, writing test sequences, and collaborating with RTL designers. Requires knowledge of simulators, regression systems, and a customer-focused attitude.

Seeking a Principal Physical Design Engineer with ≥10 years of experience in supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Must have hands-on knowledge of synthesis, place and route, timing, extraction, and other backend tools for technologies 16nm or less. Experience with Cadence and/or Synopsys tools, System Verilog/Verilog, DFT tools, and IP vendors required. Salary based on experience level.

As a Principal DFT (Design for Test) Engineer at Astera Labs, you will be responsible for developing the next generation of connectivity products, supporting cloud service providers and OEMs. You will be involved in the full product life cycle and collaborate with various engineering teams. Ideal candidates should have extensive experience in semiconductor companies and hands-on expertise with DFT techniques and tools.

Seeking a Principal Design Verification Engineer with extensive experience in PCIe and CXL protocols to drive functional verification of designs, develop test plans, write test sequences, and collaborate with RTL designers.