Search the 11 jobs at SiFive Inc

As a Staff Formal Verification Engineer at SiFive, you will be responsible for identifying blocks for Formal Verification, creating test-plans, implementing and maintaining verification environments, applying FV techniques, debugging RTL, guiding team members, automating verification processes, reviewing setups with teams, and extending assertion libraries.

Responsible for building and maintaining the Emulation hardware infrastructure, setting up CI pipelines, defining tool flows, collaborating with teams, monitoring platform efficiency, leading a team of engineers, and working with emulation vendors. Requires 12+ years of experience with expertise in SOC design, emulation systems, and various programming languages.

Identify and apply Data-Path Formal Verification techniques to optimize digital hardware design. Train team members, develop automation scripts, and collaborate with design and verification teams to ensure successful verification processes.

Staff Engineer role at SiFive involving hands-on system Verilog/UVM development work for modern high performance CPU verification. Responsibilities include writing test cases, using test generators, and working with internal test generators to target coverage/test-plan scenarios.

Develop and maintain Customer Test bench, integrate feature requirements, maintain CI/Jenkins, collaborate with teams, address inefficiencies with innovative solutions

As a Physical Design Engineer at SiFive, responsible for implementing and optimizing RISC-V CPU's, closing ambitious performance, power, and area goals, collaborating with teams, and contributing to physical design flow development.

Lead implementation and optimization of high-performance Out of Order RISC-V CPU's from RTL to GDSII. Collaborate with microarchitecture and RTL teams to achieve ambitious performance, power, and area goals. Contribute to physical implementation flow development for best automation and PPA.

Drive timing convergence of high performance designs, contribute to timing methodology development, develop timing analysis infrastructure, and work with RTL and physical design teams. Experience in Static Timing Analysis with multiple tape outs required. Strong understanding of timing tools and methodologies.

Seeking a Power Engineer with 3+ years of experience in power simulation, modeling, ASIC power analysis and optimization. Must have strong problem-solving skills and experience with low power architecture and power optimization.

Hands on System Verilog/UVM development work for modern high performance CPU verification. Writing test cases and using test generators for RISC-V CPU verification. Working with internal test generators to target coverage/test-plan scenarios.

Lead the implementation and optimization of high-performance RISC-V CPUs, collaborate with microarchitecture and RTL teams, develop physical implementation flow, and improve Foundation IP automation. Requires 12+ years of physical implementation experience and expertise in PPA optimization.