At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
As a core member of the PHY Design team, your responsibilities will span across various aspects for the ASIC frontend flow, which includes RTL development, RTL integration, maintain the timing constraint, Synthesis, Static timing analysis (STA), timing closure, power optimization, and physical verification for both of block and Chip top level
You will mainly work on PHY RTL development and also be responsible the verification debug and participating in silicon bring up with the validation team.
Job requirement:
BSEE and at least 3 years of prior RTL develop experience required. MSEE and at-lest 1 years of prior RTL experience strongly preferred.
Prior experience RTL design of high-speed interfaces.
Prior experience of collaborating with Physical Design teams in multiple successful ASIC/IP tapeouts.
Strong ability on RTL debug , and logic development.
Knowledge of the IP/SoC level timing closure flow and methodology.
Strong command of synthesis, STA, design for test, and design methodologies
Ability to handle multiple projects/tasks successfully
Experience in IP/ASIC timing constraints generation and timing closure.
Strong background in Constraint analysis and debug, using industry standard tools.
Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and Bist testing.
Team player with a passion to innovate and can-do attitude.
Self-starter and highly motivated.
Desired skills
Knowledge of DDR/GDDR DRAM protocol; high-speed PHYs
Experience designing or integrating IP
Experience in high speed and low power digital design using advanced deep micron process.
Experience with highly configurable designs
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