The Principal Design Engineer will create AMS testbench, develop verification strategies, mentor juniors, and lead a team in mixed-signal verification.
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Principal Engineer T4
Job responsibilities:
The engineer should have prior experience in most of the below responsibilities or keen to adapt
Technical
- Digital/DMS/AMS testbench creation and generation
- Behavioral Modeling in SV-RNM and Model Validation Methodologies
- Define AMS VPLAN for an IP to make sure all AMS features are covered in DV
- Create Test strategy of replicating Silicon non linearities behavior on Analog signals such as jitter, noise effect, ISI
- Mixed-Signal Assertions and Checkers
- Power intent verification including Low power states, state retention and CPF/UPF integration
- Push technology for mixed-signal modeling, simulation and DV in order to improve mixed signal verification efficiency and accuracy.
- Ensure scalable mixed-signal DV solutions to cover the breadth of IPG offerings including SerDes, DDR, A2D converters and custom solutions
- Mentor junior engineers technically and collaborate closely with Digital, Analog, Firmware and Test engineers , Internal methodology and tool development teams, such as, Virtuoso/ADE/Xcelium, PDK teams and Customer management and engineering support teams
- Able to develop, run CO-SIMULATION for verification of Analog features
- Lead and guide a team of 4-5 AMS engineer
- Document the necessary methodology and test plan developed for better knowledge sharing among teams.
We’re doing work that matters. Help us solve what others can’t.
Top Skills
Ade
Cpf
Pdk
Sv-Rnm
Upf
Virtuoso
Xcelium
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