The Principal Design Engineer will lead mixed-signal verification and modeling, mentor junior engineers, create test strategies for analog signals, and develop scalable DV solutions. Responsibilities include managing technical teams, collaborating across disciplines, and documenting methodologies for knowledge sharing.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Principal Engineer T4
Job responsibilities:
The engineer should have prior experience in most of the below responsibilities or keen to adapt
Technical
- Digital/DMS/AMS testbench creation and generation
- Behavioral Modeling in SV-RNM and Model Validation Methodologies
- Define AMS VPLAN for an IP to make sure all AMS features are covered in DV
- Create Test strategy of replicating Silicon non linearities behavior on Analog signals such as jitter, noise effect, ISI
- Mixed-Signal Assertions and Checkers
- Power intent verification including Low power states, state retention and CPF/UPF integration
- Push technology for mixed-signal modeling, simulation and DV in order to improve mixed signal verification efficiency and accuracy.
- Ensure scalable mixed-signal DV solutions to cover the breadth of IPG offerings including SerDes, DDR, A2D converters and custom solutions
- Mentor junior engineers technically and collaborate closely with Digital, Analog, Firmware and Test engineers , Internal methodology and tool development teams, such as, Virtuoso/ADE/Xcelium, PDK teams and Customer management and engineering support teams
- Able to develop, run CO-SIMULATION for verification of Analog features
- Lead and guide a team of 4-5 AMS engineer
- Document the necessary methodology and test plan developed for better knowledge sharing among teams.
We’re doing work that matters. Help us solve what others can’t.
Top Skills
Sv-Rnm
Similar Jobs
Cloud • Hardware • Software • Semiconductor
The Principal Design Engineer at Cadence will leverage their expertise in computer architecture, embedded programming, and high-performance algorithm design to contribute to innovative technology solutions. Responsibilities include coding, debugging, and optimizing software for embedded processors, while also collaborating with diverse teams and engaging with customers to resolve issues.
Top Skills:
CC++
Cloud • Hardware • Software • Semiconductor
As a Principal Design Engineer at Cadence, you will be responsible for AMS design specifically focusing on high-speed Memory PHYs. You will define designs, mentor team members, participate in cross-functional discussions, and ensure design quality and project timelines while improving methodologies for efficiency.
Top Skills:
Vlsi
Cloud • Hardware • Software • Semiconductor
The Senior Principal Design Engineer at Cadence will work on cutting-edge electronic designs, focusing on the architecture of embedded processors, high-performance algorithms, and low-level firmware programming. Responsibilities include writing and debugging software on emulation platforms, collaborating with diverse teams, and engaging with customers for resolution of issues.
Top Skills:
C,C++
What you need to know about the Bengaluru Tech Scene
Dubbed the "Silicon Valley of India," Bengaluru has emerged as the nation's leading hub for information technology and a go-to destination for startups. Home to tech giants like ISRO, Infosys, Wipro and HAL, the city attracts and cultivates a rich pool of tech talent, supported by numerous educational and research institutions including the Indian Institute of Science, Bangalore Institute of Technology, and the International Institute of Information Technology.
