The Principal Design Engineer will be responsible for leading design verification projects from concept to closure, focusing on functional verification fundamentals and environment development. The role requires a strong background in UVM and System Verilog coding and a minimum of 8 years of experience in design verification.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
- 8+ years of Design Verification experience with SV/UVM
- Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
- Design Verification experience verifying complex designs and leading projects from concept to verification closure.
- Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.
Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.
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Top Skills
Sv
System Verilog
Uvm
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