The Principal Design Engineer at Cadence will work on high-speed Serdes and memory interface circuits, lead complex IP projects, manage cross-functional teams, mentor junior engineers, and ensure excellent communication while solving complex design challenges in advanced technology nodes.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Title: Principal Design Engineer
Location: Bangalore
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
The Cadence Advantage
- The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
- Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
- The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
- Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
- You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.
Job responsibilities:
-
Experience level: 10-15 years
Education: BE/ B Tech/ ME/ M Tech / MS
- In-depth understanding of high-speed Serdes/Memory interface circuits like I/O’s,PLL’s, Clocking, Datapath’s.
- Hands on experience on PCIe Gen3/4/5/6, GDDRx/DDRx/LPDDRx memory interface circuits.
- Strong Analog Design and I/O Design fundamentals. Knowledge of ESD/Reliability/SI/PI.
- Experience in leading complex IP’s , managing cross functional dependencies needed.
- Experience in leading and mentoring Junior Engineers.
- Must have excellent written and verbal communication skills as well as good problem-solving skills.
- Prior experience of working on cutting edge technology nodes like 16nm/10nm/12nm/7nm is added advantage.
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Top Skills
Esd
High-Speed Serdes
Memory Interface Circuits
Pcie Gen3
Pcie Gen4
Pcie Gen5
Pcie Gen6
Pi
Reliability
Si
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