The Staff Design Engineer will develop components for Aeva's 4-D Lidar processing chip, focusing on RTL design, implementation of SOC functionality including DSP designs and debugging complex systems. They will collaborate with various engineering teams to ensure optimal performance and power efficiency.
Role Summary:
As a key player on the Design team, you will participate in the RTL design and development of the signal processing path for Aeva’s 4-D Lidar processing chip. You will be responsible for implementing and/or integrating sub-components of the design in ASIC.
What you'll be doing:
- Develop sub-components of the digital signaling pipeline.
- Code RTL, Test, and Validate Aeva-specific sub-components.
- Implement additional SOC functionality including functional safety and robustness functions.
- Focus on developing efficient, highly reliable, highly available, robust functionality.
- Work with Architects, design engineers, verification engineers, and System software teams to ensure that the SOC meets its functional, performance, and power targets.
What you'll have:
- 10+ years of experience in the design and verification of advanced ARM or similar processor Architecture based SOCs
- Experience and knowledge of DSP designs, algorithms, and signal processing functionality. Ability to achieve high performance and low power targets.
- Experience writing Verilog RTL Code.
- Working experience and knowledge in AMBA protocols, LPDDR, Ethernet, MIPI, and high-speed Serdes etc.
- Proficient in debugging complex SOC or CPU core designs
- Desire to learn & implement groundbreaking new processes and methodology for continuous improvement
Nice to haves:
- Experience in FPGA designs, pre-silicon validation on emulation platforms such as Cadence Palladium, Mentor Veloce, Synopsys Zebu
- Post-silicon bring-up and validation planning and execution
- Diagnostics Firmware development and validation
Top Skills
Verilog
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