The Senior Hardware Verification Engineer plans, develops, and executes ASIC/SoC verification to ensure functional correctness through UVM-based environments and test plans.
The Senior ASIC Hardware Verification Engineer is responsible for planning, developing, and executing verification of ASIC/SoC designs to ensure functional correctness prior to tape-out. This includes building UVM-based environments, creating test plans, developing testcases, achieving coverage closure, and debugging complex hardware issues.
Verification Planning
Testbench Development
Test Development and Execution
Functional Coverage and Closure
Assertion-Based Verification
More information about NXP in India...
#LI-2734Top Skills
Asic
Debugging
Soc
Test Plans
Uvm
Verification
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