Senior Staff DFT Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Central Engineering (CCDS) - ASIC India in Marvell is a Custom Logic Design and Methodology group responsible for delivering complex ASIC chips. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements.

What You Can Expect

• Capability to lead a project for DFT full chip activity and for block level closure

• Develop architecture and implementation for new DFT features, enhancing existing features , bug fixing

• Work on latest technology & synopsis tool flow wrt DFT implementation, ATPG and DFT verification

• Optimizing test time, test area and test power and coverage improvement to enhance performance

• Trouble shooting and solving issues/bugs reported by peer or by customer

• Able to support Juniors for their development , and collaborate with them for project work.

What We're Looking For

Bachelor’s/Masters degree in Computer Science, Electrical Engineering or related fields and 7-10 years of related professional experience.

The candidate Marvell is looking for will have:

• Very good knowledge on SCAN/ATPG/JTAG/MBIST

• Good Knowledge and understanding on JTAG for IEEE1149.1/6 standards

• Proficiency in Industry standard Tools for Scan insertion, ATPG, MBIST and JTAG. (Preferably Synopsys/Mentor tools)

• Proven experience on Test structures for DFT, IP Integration, ATPG Fault models, test point insertion, coverage improvement techniques

• Proven experience in Scan insertion techniques at block level and Chip top level

• Good hands on experience on Memory BIST generation, Insertion, verification on RTL/Netlist level

• Cross domain knowledge to resolve DFT issues with design, synthesis, Physical design, STA team

• Good knowledge on Perl/ Tcl scripting 

• Proven experience on gate level simulations with no timing and SDF based simulations

• Experience with Post-Si ramp up and debug on ATE

• Should be able to independently own and delivery tasks that are assigned

• Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization

• High sense of responsibility and ownership within the team for successful Tapeout and Post -Si ramp up of the project

#LI-RS1

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.