Develop and maintain verification environments using UVM, define test plans, and ensure design verification while collaborating with teams.

You will lead the egress processor IP design, implement specifications using RTL, collaborate with teams on various tasks, and ensure quality criteria are met.

Develop and maintain verification environment in UVM, work with architecture and design teams to define test plans and verify designs, driving verification to meet coverage targets.

The Principal Physical Design Engineer will manage physical design and methodology for next-gen processor chips, performing synthesis, place and route, and timing analysis while collaborating with various teams.

Manage environmental, health, safety, and sustainability strategies across Marvell's regional offices in India. Ensure compliance, foster training, and promote sustainability initiatives.

Design and verify sophisticated CMOS transceivers and essential analog IPs for AI, Datacenter, and Automotive applications while collaborating with cross-functional teams and mentoring junior engineers.

The Principal Engineer will architect and implement DFT/Test solutions for complex ASIC/SoC designs, leading a team and enhancing methodologies.

The Staff Engineer will work on the physical design and methodology for high-performance processor chips, focusing on place and route flows using EDA tools, collaborating with RTL design teams, and addressing timing and logic issues to enhance design processes.

Lead and implement DFT/Test on complex SoCs, mentor engineers, and enhance methodologies for ASIC/SoC designs.

The Senior Staff Engineer, DFT will work on DFT architecture, testability strategy, implementation and verification of DFT features in Marvell's Switch products, collaborating with various teams for effective integration and validation.

The Design Verification Director leads a team of engineers in ASIC verification, manages projects, mentors staff, and collaborates across teams to ensure quality deliverables for high-performance products.

The Staff Engineer will lead physical design methodologies for next-generation processor chips, focusing on Place and Route Flow and timing analysis while collaborating with global teams.

The Staff Engineer will work on Design for Testability in networking products, collaborating with various teams on architecture, implementation, and verification tasks.

The Cyber Threat Hunting and Intelligence Analyst will identify and respond to cyber threats, conduct threat hunting, develop detection logic and playbooks, and provide expert threat analysis for Marvell's cybersecurity operations.

Develop and maintain verification environments, define test plans, verify design functionality, debug failures, and analyze coverage metrics in a team setting.

Lead the ASIC design physical implementation team, managing multi-million-gate hierarchical designs, optimizing workflows, and mentoring engineers while working on cutting-edge technology nodes.

The position involves working on physical design and methodology for next-generation processor chips, utilizing EDA tools for synthesis and timing analysis, collaborating with teams globally, and mentoring juniors.

The Senior Staff Power Design Engineer will work on ASIC design, collaborating across teams on low power design and implementation, ensuring optimal power performance across various technologies.

The role involves physical design for ASICs, focusing on complex chip implementation, synthesis, timing analysis, and collaboration with teams to ensure success in tapeouts.

As a Staff Signal Integrity Engineer, you will collaborate with various engineering teams, perform simulations, analyze schematics, guide PCB layouts, and ensure the accuracy of hardware designs for data processing products.