Senior Technologist, ASIC Development Engineering - Physical Design Lead (Full Chip)

Company Description

At Western Digital, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible.

At our core, Western Digital is a company of problem solvers. People achieve extraordinary things given the right technology. For decades, we’ve been doing just that. Our technology helped people put a man on the moon.

We are a key partner to some of the largest and highest growth organizations in the world. From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter and more connected, to powering the data centers behind many of the world’s biggest companies and public cloud, Western Digital is fueling a brighter, smarter future.

Binge-watch any shows, use social media or shop online lately? You’ll find Western Digital supporting the storage infrastructure behind many of these platforms. And, that flash memory card that captures and preserves your most precious moments? That’s us, too.

We offer an expansive portfolio of technologies, storage devices and platforms for business and consumers alike. Our data-centric solutions are comprised of the Western Digital®, G-Technology™, SanDisk® and WD® brands.

Today’s exceptional challenges require your unique skills. It’s You & Western Digital. Together, we’re the next BIG thing in data.

Job Description

Job Summary:

We are seeking a highly skilled and experienced Physical Design Lead with expertise in full-chip Redistribution Layer (RDL), bump, and packaging interface. The ideal candidate will lead the physical design efforts of our advanced semiconductor products, ensuring optimal performance, manufacturability, and reliability. This role involves close collaboration with cross-functional teams, including design, manufacturing, and packaging engineers.

Key Responsibilities:

- Drive the full-chip physical design process, including floor planning, placement, routing, and timing optimization. Ensure design meets performance, power, area, and manufacturability requirements. Manage and guide a team of physical design engineers, providing technical direction and mentorship.

- Develop and optimize full-chip RDL and bump layouts. Collaborate with packaging and manufacturing teams to define bump patterns and RDL structures. Ensure robust design solutions that meet electrical and mechanical constraints.

- Work closely with packaging engineers to ensure seamless integration between chip design and package. Define and optimize die-to-package interconnects, including considerations for signal integrity and thermal management. Address challenges related to package constraints and contribute to innovative packaging solutions.

- Interface with RTL designers, DFT engineers, and verification teams to ensure design consistency and compliance with project specifications. Collaborate with process engineers to understand and integrate process variations and constraints. Participate in design reviews and provide critical feedback to improve overall design quality.

- Conduct thorough design rule checks (DRC), layout versus schematic (LVS) checks, and electrical rule checks (ERC). Perform timing analysis, power analysis, and signal integrity checks to validate design robustness. Ensure design meets all tape-out criteria and coordinate with foundry partners for successful fabrication.

- Stay updated with the latest advancements in physical design tools, methodologies, and technologies. Implement best practices and drive continuous improvement in design processes and methodologies. Contribute to the development of in-house tools and scripts to enhance design efficiency and quality.

Qualifications

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

- Minimum of 12+ years of experience in physical design, with a focus on full-chip RDL, bump, and packaging interface.

- Proven track record of leading physical design projects from concept to tape-out.

- Strong knowledge of physical design tools and methodologies (e.g., Cadence, Synopsys etc).

- Expertise in floor planning, placement, routing, timing analysis, and DFM.

- Familiarity with packaging technologies and die-to-package interconnects.

- Excellent problem-solving skills and attention to detail.

- Strong communication and teamwork skills, with the ability to work effectively in a collaborative environment.

- Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable.

Additional Information

Western Digital thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.

Western Digital is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.