Search the 31 jobs at Cadence Design Systems

Senior Solutions Engineer role at Cadence focusing on safety solutions using Cadence Verification Safety Solution. Responsibilities include driving deployment of Functional Safety Solution at Customer Place and guiding customers to achieve safety goals.

Cadence is hiring a Memory Design Engineer with 15-25 years of experience to work in their Memory IP team in Hyderabad. The responsibilities include circuit design, simulation, verification, and silicon bring-up for memory design blocks. Proficiency in Cadence, Mentor Graphics, and Synopsys tools is required, along with good technical communication and teamwork skills.

Work with the Cadence global IC design team to develop semiconductor IP for top electronic product companies, ensuring continuous quality improvement and adherence to quality procedures.

Lead Design Engineer responsible for creating and maintaining functional verification environments, defining verification strategies, and collaborating with cross-functional teams. Requires expertise in Verilog, SystemVerilog, UVM methodology, RTL, and various verification domain skills. Desirable skills include power-aware RTL, formal verification, gate-level simulations, and exposure to automotive IP verification.

The Sr. Principal Software Engineer at Cadence will be responsible for UI/UX development in React.js, optimization of website performance, integration with backend services, creating data visualizations, and backend infrastructure development.

Join a growing team at Cadence as a Sr Principal Design Engineer, responsible for leading the Design for Test activities for next-gen SoCs. Define DFT architecture, implement verification logic, collaborate with teams, and work on silicon bring up. Ideal candidate has 8-15+ years of experience with key DFT concepts and working knowledge of Verilog coding

Looking for a Senior Principal RTL Design Engineer with 12+ years of ASIC design experience. Proficiency in Verilog coding, RTL design, and various interface protocols. Must have knowledge of RTL checks and synthesis flow.

Maintain/upgrade infrastructure/automation for RTL development and design-verification teams at multiple locations using multiple server farms. Manage/monitor regression trends, automate error/defect reporting, and support users in various server farms.

Perform formal verification of design for complex IPs, subsystems, and SoCs using Jasper App. Define and improve design and verification methodologies for formal verification closure. Partner with customers to build innovative formal solutions and drive new capabilities/features with R&D team.

Cadence is looking for a passionate Layout Design professional with 2-14 years of experience in Analog Layout and SerDes IP. The role involves working on cutting edge FinFET technologies and collaborating with Tier-1 customers. Responsibilities include hands-on layout experience in various analog IPs, knowledge of layout effects on circuits, understanding of DSM technology, and communication skills. Scripting and automation experience is a plus.

As an Application Engineer at Cadence, you will provide technical consultation for digital & sign-off domain products to customers worldwide. You will work closely with customers to understand and debug complex issues, guide them in leveraging the latest tool capabilities, and help with software implementation in their design methodologies. This role also involves contributing to product improvement initiatives and creating knowledge content.

As a Principal Application Engineer at Cadence, you will partner with customers to provide post-sales technical consultation for digital & sign-off domain products. You will work closely with customers to understand and debug complex issues, help them leverage the latest tool capabilities, and guide them in implementing software in their design methodologies. This role offers the opportunity to acquire technical knowledge, exposure to industry best practices, and contribute to product improvement initiatives.

The Sr. Principal Product Engineer at Cadence will work on signoff Timing and ECO tools, collaborate with team members to address customer issues, interact with R&D and Key Technologists, and develop new technologies. The role requires expertise in Timing Signoff/Digital Implementation and strong communication skills.

Lead Product Engineer responsible for driving the development of products and technologies in the Memory domain of Verification IP family. Must have strong verification expertise, understand customer design and verification flows, and support pre-sales technical activities. Additionally, collaborate with various teams to ensure product alignment and provide training to field engineers and customers.

Principal DFT Design Engineer responsible for mentoring junior engineers, driving innovation/automation, working with cross-functional teams, and leading DFT methodology advancements to improve quality and reliability.

Senior Solutions Engineer role at Cadence focused on safety solutions using Cadence Palladium Emulation solution. Responsibilities include partnering with semiconductor customers to develop methodologies, diagnose verification problems, and guide them to achieve safety goals.

Managing a SerDes DV group focusing on MDV verification, customer interactions, technical alignment, and developing new verification methodologies. Strong background in functional verification fundamentals and experience in serial bus multiprotocol PHY IPs like PCIe. Expertise in Verilog, SV, e with UVM/OVM/eRM methodology, assertions development, RTL, GLS sim debug, and more. Desirable skills include power-aware RTL set-up, formal verification, gate-level simulations, and exposure to Analog modelling and Automotive IP verification.

Lead Education Application Engineer responsible for designing and developing training materials, delivering courses, creating online educational videos, and providing support to customers. Requires strong knowledge of analog and mixed-signal design and Cadence design tools. Bachelor's or Master's degree in Electrical/Electronics Engineering and 4-6 years of related experience.

Develop and implement comprehensive PDN analysis methodologies for complex 3DIC packages, analyze and optimize signal integrity for high-speed interfaces, collaborate with cross-functional teams to optimize PDN design and heat dissipation, propose innovative solutions for power integrity performance, and provide expert guidance on signal/power integrity matters.

As a Lead Application Engineer at Cadence, you will partner with semiconductor customers to drive innovative methodologies for cutting-edge designs. You will influence product direction, work with sales teams, and deploy ML solutions to improve productivity. This role offers a supportive environment focused on technology and innovation.