Top Tech Jobs & Startup Jobs in Bengaluru, KA

Collaborate with design and verification teams, integrate design verification processes, acquire new skills, meet deadlines, share knowledge, maintain professionalism, and embrace company culture. Requires proficiency in Verilog and related languages, analog circuits, digital design, PMIC knowledge, simulation debugging, Unix environment, and communication skills.

Senior project lead responsible for design verification of analog & mixed signal design using advanced methodologies. Lead verification of complex integrated circuits, develop verification strategies, mentor team, and contribute to company's verification strategy.

The Sr Manager AMS Design Verification Engineering role at Renesas involves serving as the main point of contact between local and US-based teams, facilitating collaboration, integrating verification processes, building and leading a high-performing team, conducting performance reviews, monitoring project progress, and representing the team in strategic discussions.

Collaborate with design and verification teams to achieve first-pass silicon success and performance goals. Responsible for integrating design verification processes and assisting in meeting project deadlines with high-quality deliverables. Requires 5+ years of experience in mixed-signal IC design and verification with proficiency in Verilog, SystemVerilog, VerilogAMS, UVM, and Unix environment.

Collaborate with design and verification teams to achieve first-pass silicon success and performance goals. Proficient in Verilog and SystemVerilog, with strong understanding of analog circuits and digital design processes. Excellent simulation debugging skills and Unix environment knowledge required.

Collaborate with design and verification teams, integrate processes for silicon success, demonstrate willingness to acquire new skills, meet deadlines, share knowledge, maintain professionalism, embrace company culture, proficient in Verilog, SystemVerilog, VerilogAMS, Unix, shell scripting, Python.

Collaborate effectively with design and verification teams, integrate processes for silicon success, meet deadlines, and share knowledge with team members. Requires 5+ years of mixed-signal IC design experience and proficiency in Verilog, SystemVerilog, VerilogAMS, UVM.