Top Python Jobs in Bengaluru

Lead and grow the India engineering team (initially 5 engineers) across product, SRE, and InfoSec; own technical roadmap, drive scalable secure systems, mentor and hire, partner with US product and data teams, and implement engineering best practices for reliability and incident response.

Design, build, test, and deploy smart contracts and decentralized applications. Maintain blockchain integrations and backend services, optimize for security and gas efficiency, contribute to architecture and technical strategy, conduct code reviews, mentor junior engineers, and collaborate with product, frontend, and security teams.

As a Senior Software Engineer, you will design and implement workflow systems, build orchestration layers, and mentor junior engineers while ensuring reliable and observable AI workflows.

Drive the infrastructure strategy for AI platform, leading a DevOps team for critical systems in regulated environments, focusing on cloud, Kubernetes, observability, and security operations.

Design, build, and maintain automated CI/CD pipelines (migrating from Octopus to Harness) using tools like Bitbucket, Bamboo, Jenkins, Docker, Kubernetes and Helm. Automate deployments, script in Groovy/Powershell/Ansible/Python, document requirements, improve monitoring, and collaborate with development and QA across the SDLC.

As the Founding Cloud Infrastructure Engineer, you'll design secure cloud infrastructures using AWS/Azure/GCP, support distributed AI workloads, manage GPU resources, and collaborate on ML initiatives.

The Backend Engineer will design, implement, and scale microservices for AI and data platforms, defining service boundaries and APIs while contributing to deployment infrastructure.

Lead development and ownership of full-chip STA sign-off methodology and timing convergence strategy. Architect and deploy STA/ECO flows, benchmark EDA tools (Cadence Tempus), build automation (Tcl/Python/Perl), define MMMC and margin strategies, and collaborate with RTL, CAD, DFT, and Physical Design to meet PPA and tape-out goals.

Design, build, and maintain high-performance, low-latency distributed backend systems and microservices. Implement RESTful APIs, data stores, messaging, and monitoring. Drive architecture, CI/CD, cloud operations, code reviews, mentoring, and scaling to support hundreds of millions of users.

Develop and integrate OCP SAI with SONiC, enhance control plane stack, ensure optimal SDK performance, and create automated test tools.

Develop SDK bridging hardware and software for networking. Ensure performance of switch ASICs with a focus on L2/L3 protocols and embedded systems.

Build and maintain CI/CD pipelines, design and manage AWS cloud infrastructure, run Docker and Kubernetes platforms, improve release automation and observability, support incident response, and scale infrastructure for microservices and AI/ML workloads while improving developer experience and security.

Lead the QA function: define QA strategy, build scalable automation frameworks, design and execute UI/API/performance tests, integrate tests into CI/CD, mentor QA engineers, and ensure high reliability for data-intensive fintech systems.

As a Staff Platform Engineer, you will lead the architecture and automation of cloud-native platforms, enhance operational reliability, and mentor engineers while leveraging Azure and DevOps methodologies.

As a Senior Staff Software Engineer, you'll shape the architecture of JazzX's AI-native platform, ensuring scalability, reliability, and performance. You'll lead design reviews, guide cloud-native practices, enhance developer experience, and ensure operational excellence, while also mentoring other engineers and collaborating with cross-functional teams to deliver robust capabilities.

Lead the design and development of an innovative enterprise AI platform, mentoring junior engineers and ensuring operational excellence.

As a Senior AGI Engineer, you will develop AGI solutions, integrate features in client environments, and collaborate across teams to deliver measurable results.

Design, build, and operate highly available AWS cloud infrastructure and Kubernetes (EKS) clusters. Implement IaC (Terraform/CloudFormation), Helm charts, CI/CD pipelines, and automation in Python. Support high-throughput Kafka/SQS data pipelines, enforce DevSecOps practices (SAST/DAST, container scanning, IAM, encryption), and deploy observability stacks (Prometheus, Grafana, ELK, Datadog) to ensure platform reliability and 99.9% uptime.

Design and lead development of miniaturized PCBs for wearable devices using custom Wi-R ICs and COTS components. Create schematics and layouts, perform board-level testing and debugging, collaborate on packaging, and support prototype validation and test automation.

Work on a large enterprise codebase supporting corrugated manufacturing operations. Develop and maintain Java 17/Java EE applications, deploy on TomEE/OpenEJB, design and optimize SQL Server schemas and queries, build/consume REST APIs, and use Windows/Eclipse, PowerShell, and Git for development, build, and deployment tasks.

Lead architecture, design, and delivery of reusable digital and mixed-signal IPs. Manage and mentor IP design teams, drive microarchitecture and verification, ensure PPA and quality targets, coordinate cross-functional SoC integration, oversee program schedules and risk mitigation, and support silicon bring-up and customer issue resolution.

Lead microarchitecture and RTL design of high-performance SoC subsystems for AI/cloud connectivity. Drive RTL development in Verilog/SystemVerilog, optimize PPA and testability, collaborate cross-functionally for timing closure, silicon bring-up, and post-silicon debug, and mentor engineering teams while advancing IP reuse and design methodologies.

Lead verification strategy and execution for complex connectivity IPs and SoCs (CXL/PCIe/Ethernet). Architect and develop UVM/SystemVerilog environments, drive coverage-driven constrained-random verification, debug RTL/protocol/timing issues, build reusable VIP, and mentor teams to achieve first-pass silicon success.

Lead RTL design and implementation of complex digital IPs and SoC subsystems for high-performance connectivity products. Own specification-to-silicon flow, design synthesizable Verilog/SystemVerilog, develop datapaths, control logic and protocol engines (CXL, PCIe, Ethernet, AXI). Collaborate with verification, physical design, firmware, and system teams; support synthesis/lint/STA/DFT, debug silicon issues, and mentor engineers.

Lead verification of complex IPs and SoC subsystems from spec through tape-out. Own verification planning, UVM/SystemVerilog environment development, test execution, coverage closure, debugging, root-cause analysis, and sign-off. Collaborate with architecture, design, firmware, emulation, and validation teams and mentor engineers to ensure high-quality, first-pass silicon.